Speaker: Dr. Tomasz Brozek, Technical Fellow and Engagement Director at PDF Solutions, San Jose, CA

Date: Tuesday, June 13th, 2017

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments

6:15 – 7:00 PM: Seminar 

Cost: Free

Location: Texas Instruments Building E Conference Center
2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building location map and directions

Contact: Victor Cao

Web link: http://site.ieee.org/scv-eds/

Abstract:

Keeping Moore’s Law alive requires continuous scaling of both geometrical dimensions and operating voltage. Device and process variability are usually main limiters of scaling, and serious challenge in advanced technology generations. They impact the yield of Integrated circuits, both Parametric and Functional components. The Tutorial will discuss the sources of variability, their decomposition, and characterization. In addition to transistor variability, variability of process modules in FEOL, MOL, and BEOL will be briefly discussed. Finally, characterization approaches, and examples will be provided.

Biography:

Dr Brozek is a Technical Fellow and Engagement Director at PDF Solutions, San Jose, California. He earned his M.S. EE degree from Lvov Technical University and Ph.D. degree in Physics from Institute of Semiconductors, Academy of Sciences in Kiev. He worked as Assistant Professor and lead research projects in physics and technology of MOS devices at Warsaw University of Technology, Poland and at University of California, Los Angeles. Tomasz has been with PDF since 2000 and focused on process characterization, technology integration, yield improvement, and reliability. He has served as Engagement Manager for several successful PDF yield ramp projects in the past. He has been working on projects with advanced CMOS, NVM FLASH, DRAM, MOS Image Sensors. Before joining PDF Tomasz was with Motorola, working on device characterization, charging damage, process assessment, and reliability support for technology development and transfer of Logic, BiCMOS, and embedded FLASH technologies.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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