Past Events
Past Events
Welcome to Electron Devices Society–Santa Clara Valley/San Francisco Chapter
======================================================================
Heterogeneous Integration for AI Architecture
The IEEE Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is co-hosting this Electron Devices Society Distinguished Lecture.
When/Where: Friday Nov 1, 2024, 09:00AM Pacific Time Zone
Registration: Link
Contact: hiuyung.wong at ieee.org
Speaker: Dr. Mukta Farooq, IBM
Abstract:
While silicon scaling has reached astonishing levels over the last half century, there has not been a corresponding level of scaling in electronic packaging technology. However, Artificial Intelligence (AI) architectures are now changing the landscape, increasingly moving us towards advanced packaging technology and Heterogeneous Integration (HI). What are these unique requirements of AI which are driving the need for HI? What are some of the unique challenges in semiconductor and packaging technologies that must be overcome to make this successful? This seminar will discuss key HI methods including interposers, fan out wafer level processing, silicon bridges, and 3D integration to see how they can be leveraged to achieve AI architectures
======================================================================
POTENTIAL AND CHALLENGES IN GALLIUM OXIDE, THE NEXT GENERATION POWER SEMICONDUCTOR TECHNOLOGY
The IEEE Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is co-hosting this event with the IEEE Power Electronics Society of the SCV/SF/OEB chapter.
When/Where: Tuesday 29 Oct 2024, 06:30 PM to 08:00 PM Pacific Time Zone
Contact: hiuyung.wong at ieee.org
Speaker: Dr. Uttam Singisetti
Abstract:
The monoclinic gallium oxide (Ga2O3) (bandgap 4.8 eV) is one of several ultra-wide bandgap semiconductors (UWBGs) that have garnered a lot of interest as next generation power semiconductor technology. Since the first demonstration of a MESFET in 2012, Ga2O3 device research has progressed at an incredible pace with reports of MOSFETs and diodes achieving 10 kV breakdown voltages. Gallium oxide devices have also achieved impressive high power device figure of merit, high average field strengths and high-speed performance. The high critical electric field, good electron mobility, multiple shallow donors, availability of large area substrates and growth of high-quality epitaxial films; have all contributed to the rapid progress in device performance. As a result, it has emerged as a promising ultra-widebandgap semiconductor for next generation power, GHz switching and RF applications. In addition to the large Baliga’s Figure of Merit (BFoM); good electron mobility, calculated electron velocities lead to higher Johnston’s Figures of Merit (JFoM). Additionally, the large bandgap also enables high temperature operation and radiation hardness making it attractive for space applications such as Mars and Venus missions. This talk will present the most recent advances in gallium oxide devices; both from our group and others. We will present the lateral MOSFETs with improved field plate design and beyond-kV breakdown. Temperature dependent analysis and device simulation suggest an extrinsic breakdown mechanism outside the channel. A simple and yet effective SU-8 polymer passivation technology provides a significant improvement in breakdown voltages. The higher field strength of the SU-8 polymer enables a significant increase in breakdown voltage to 8.5 kV in lateral MOSFETs. However, these devices show a high Ron, which is due to the depletion caused by RIE of the channel. We will present the use of ultra-high vacuum annealing techniques to improve the on-resistance of the devices still maintaining the multi-kilo-volt rating of the devices. We will also present on-wafer individual device level switching characteristics. I will discuss the progress made on vertical Schottky barrier diodes (SBDs) which have rapidly achieved both high voltages and high-power deice figures of merit. Several groups have incorporated nickel-oxide/gallium oxide hetero-junction p-n diodes to successfully overcome the absence of p-doping in gallium oxide. High surge-current capability and unclamped inductive switching (UIS) have been demonstrated in these devices despite the low thermal conductivity. Finally, I will discuss the approaches that could address the challenges in this semiconductor system (low thermal conductivity and absence of p-doping). I will conclude by discussing the factors that could potentially lead to successful lab-to-fab transition in this exciting next generation power semiconductor technology.
======================================================================
USING PREDICTIVE ENGINEERING FOR MULTIPLE RESPONSE OPTIMIZATION OF AN INTEGRATED CIRCUIT
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is co-hosting Eric Maass
When/Where: Friday, 13 Sep 2024, 12PM Pacific Time Zone
Registration: Link
Contact: hiuyung.wong at ieee.org
Speaker: Eric Maass PhD
Abstract:
Engineers traditionally use deterministic modeling in their tasks, but challenges for developing and optimizing products and processes inspire us to venture beyond deterministic to probabilistic or stochastic modeling. In this continuation from the prior presentation, a case study applying predictive engineering for the optimization of 4 requirements for an integrated circuit (Integrated Alternator Regulator for automobiles) will be shared. Deterministic models were derived by using design of experiments (DOE) and response surface modeling (RSM) in concert with circuit simulations. These deterministic models were melded with probabilistic modeling using Monte Carlo Simulation and Variance Transmission. Yield Surface Modeling™ will be introduced and shared and applied for stochastic co-optimization of the four requirements of the design. Brief summaries and overviews of other applications of predictive engineering to integrated circuit design stochastic optimization will be shared.
==============================================================
2-D Materials: Innovations for Future Semiconductor Applications
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is co-hosting Prof Jeongwon Park.
When/Where: Thursday, August 22 · 11:30am – 1:15pm PDT. In-person event (Venue: Covalent Metrology Services 927 Thompson Place Sunnyvale, CA 94085)
Registration: Link
Contact: hiuyung.wong at ieee.org
Speaker: Professor Jeongwon Park (JP)
Abstract:
The rapid development of the nanoelectronic industry over the past decades has relied on the process of transistor scaling to provide significant improvements to transistor performance at a reduced cost. Multiple directions have been pursued to extend the semiconductor industry’s growing trend, including searching for new material systems, designing new transistor structures, demonstrating new functionalities, and developing new applications.
The semiconductor chip has two main elements: active devices (i.e., transistors) and interconnects.
As for active devices, new 2-D materials (MoS2, WS2, BN, etc.) are all aggressively studied to realize high energy efficiency and memory/logic functions for system compactness. Since the discovery of graphene in 2004, researchers have focused on layer-structured materials and their applications in electron devices.
This talk will present the current status and possible application developments in nanoelectronics and nanomaterials. After a brief introduction, the general nanoelectronics and 2D materials for device applications are discussed. The technical challenges of 2D materials are discussed. This talk will introduce various technologies based on 2D materials and discuss possible applications. In addition, traditional silicon-based devices and nanotechnology-enabled high-performance devices will be discussed.
=============================================================
Oxide based multilevel memristive switching devices for efficient analog In-memory computing in AI applications
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is co-hosting Dr. Glenn Ning. The title of the lecture is ‘Oxide based multilevel memristive switching devices for efficient analog In-memory computing in AI applications’
When/Where: 23rd May, 2024, Noon-1PM. In-person event (Venue: EAG Laboratories – 810 Kifer Road, Sunnyvale)
(Use corner entrance: Kifer Road / San Lucar Court. Do not enter at main entrance on Kifer Road )
Registration: Link
If you face an issue with vtools registration send an email to hiuyung.wong at ieee.org to get the zoom link and indicate whether you are an IEEE member, IEEE EDS member, IEEE Student member
Contact: hiuyung.wong at ieee.org
Speaker: Dr. Glenn Ning
Abstract:
The von Neumann architecture’s intrinsic bottleneck in data transfer between processor and memory units hinders performance as data sets continue to grow. TetraMem’s memristive devices-based analog in-memory computing significantly boosts throughput and energy efficiency in deep learning.
Our approach utilizes pre-trained synaptic weights from cloud-based training, directly programming them into computing memristors/multi-level RRAMs made with nanometer thin-films for edge deployment and enabling post-tuning to accommodate specific scenarios. High-precision programmability ensures uniform performance across memristive networks by necessitating numerous distinguishable conductance levels in each device. This advancement benefits applications like neural network training and inference computing.
By achieving stable 8 bits and above multi-levels conductance in individual memristor devices (up to 11 bits/cell, as featured in Nature), we enable monolithically integrated semiconductor chips, featuring large crossbar arrays on complementary metal-oxide-semiconductor (CMOS) circuits in the commercial foundry, suitable for diverse AI applications. Our arbitrary precision computing based on analog computing work was recently published in Science…
Speaker Bio:
Dr. Glenn Ning Ge is the CEO and co-founder of TetraMem, a leading Silicon Valley startup. With a decade of experience in the semiconductor sector, he has contributed to numerous product innovations. He boasts around 800 global patent filings, stemming from over 300 US/PCT patent families, many of which are now in mass production.
Dr. Ge holds three Master’s degrees, including an MBA from the University of Michigan’s Ross School of Business, and a Ph.D. in Electrical Engineering from Nanyang Technological University, Singapore. He is a former Board Member of the SFBA IEEE Nanotechnology Council..
Thanks to Eurofins EAG Laboratories for providing the venue for this seminar.
======================================================================
More-than-Moore miniaturisation
with graphene and cubic silicon carbide
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Francesca Iacopi. The title of the lecture is ‘More-than-Moore miniaturisation with graphene and cubic silicon carbide’
When/Where: 17th Apr, 2024, 5:30 pm – 7:00 pm. Hybrid event (Venue: Parlor B, Benson Memorial Center, Santa Clara University, 500 El Camino Real, Santa Clara, CA 95053)
(Benson Center is our student center and off-campus parking is a viable option, though not as safe as on-campus with a parking pass. We can arrange for free 2-hour parking for attendees. The parking permits can be picked up at the venue after they have parked their cars in the visitor lot)
Campus map can be found here: https://www.scu.edu/map/
Note: To attend in person and obtain a free parking permit, MUST RSVP before 4/14/2024 5PM
Registration: Link
If you face an issue with vtools registration send an email to hiuyung.wong at ieee.org to get the zoom link and indicate whether you are an IEEE member, IEEE EDS member, IEEE Student member
Contact: hiuyung.wong at ieee.org
Speaker: Prof. Francesca Iacopi
Abstract:
It is well known that harnessing graphene’s properties on a silicon platform could deliver a broad range of novel miniaturized andreconfigurable functionalities. It is less known that some key functionalities for MEMS/NEMS, nano-optics and metasurfaces can be uniquely unlocked by the combination of graphene and silicon carbide [1, 2, 3].
Over the last decade, we have developed an epitaxial graphene on silicon carbide on silicon technology that inherently delivers both capabilities. This platform allows to fabricate any complex graphene flat or 3D nanopattern in a site – selective fashion, ie without etching of the graphene, at the wafer -scale and with sufficient adhesion for integration [1, 4].
We will review the learnings from the development of this technology and some of its most promising applications. We show that the sheet resistance of epitaxial graphene on 3C-SiC on silicon is comparable to that of epitaxial graphene on SiC wafers, despite substantially smaller grains. We also indicate that the control of the graphene interfaces, particularly when integrated, can be a more important factor than achieving large grain sizes [4]. In addition, we show that well- engineered defects in graphene are preferable to defect -free graphene for most electrochemical applications. Promising examples of application of this technology in the More- than – Moore domain include integrated energy storage [5], MIR sensing and detection [6], and sensors for electro-encephalography [7, 8] for brain-computer interfaces [9]..
[1] B.Cunning et al, Nanotechnology 25 (32), 325301, 2014 [2] E.Romero et al., Physical Review Applied 13 (4), 044007, 2020 [3] P.Rufangura e
al, Journal of Physics: Materials 3 (3), 032005, 2020 [4] D.Katzmarek et al, Nanotechnology 34 (40), 405302, 2023 [4] A.Pradeepkumar et al, ACS
Applied Nano Materials 3 (1), 830-841, 2019 [5] M.Amjadipour, D.Su and F.Iacopi, Batteries & Supercaps 3 (7), 587-595, 2020 [6] P.Rufangura et
al, Nanomaterials 11 (9), 2339, 2021 [7] S.Faisal et al, Journal of Neural Engineering 18 (6), 066035, 2021 [8] S.Faisal et al, ACS Appl. Nano
Mater. 6 (7), 5440-5447, 2023 [9] F.Iacopi and CT Lin, Progress in Biomedical Eng. 4 (4), 043002, 2022.
Speaker Bio:
Professor Francesca Iacopi is an IEEE Fellow with over 20 years’ industrial and academic research expertise in semiconductor technologies, with 160 peer-reviewed publications and 10 granted US patents, spanning interconnects, CMOS devices and packaging. Her research focuses on the translation of basic scientific advances in nanomaterials and novel device concepts into implementable integrated technologies. She is known for her seminal work on the integration of porous dielectrics in on-chip interconnects, and for
the invention of the alloy -mediated epitaxial graphene platform on SiC/Si pseudo-substrates. She was recipient of an MRS Gold Graduate Student Award (2003), an Australian Research Council Future Fellowship (2012), a Global Innovation Award in Washington DC (2014) and was listed among the most innovative engineers by Engineers Australia (2018). Francesca is an IEEE EDS Distinguished Lecturer and serves regularly in technical and strategic committees for IEEE and the Materials Research Society.
She is an Elected Member to the IEEE EDS Board of Governors (2021, 2024) and serves in the Editorial Advisory Board for ACS Applied Nanomaterials, and the IEEE The Institute magazine. She is also the inaugural Editor-in-Chief of the IEEE Trans. on Materials for Electron Devices (IEEE T-MAT). She leads the Integrated Nanosystems Lab, in the Faculty of Engineering and IT, University of Technology Sydney. She is a Chief Investigator of the CoE in Transformative Meta-Optical Systems (TMOS), funded by the Australian Research Council..
======================================================================
Thermal Atomic Layer Etch for Logic and Memory Downscaling
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is co-hosting Dr. Martin McBriarty. The title of the lecture is ‘Thermal Atomic Layer Etch for Logic and Memory Downscaling’
When/Where:
11:30 AM: Networking, Pizza & Drinks
Noon — 1 pm: Seminar
In-person event (Venue: EAG Laboratories – 810 Kifer Road, Sunnyvale)
Registration: Link
Speaker: Dr. Martin McBriarty
Abstract:
As downscaling approaches physical limits, semiconductor devices are evolving into increasingly complex 3D nano-architectures. Fabricating these unprecedented devices in HVM requires precise and selective material deposition & etch methods.
Atomic layer etch (ALE) helps to sculpt these structures by selectively removing materials with angstrom-scale control. By exploiting chemical differences between materials, ALE processes are designed to etch certain exposed materials while minimizing damage to others. ALE can enable scaling boosters such as fully self-aligned via (FSAV), a critical method for logic back end of line (BEOL) downscaling. Vapor-phase thermal ALE can also provide controlled, selective etch in features with high aspect ratio, low critical dimension, or horizontal openings, overcoming the limitations of wet and plasma etches in emerging 3D structures.
This seminar will focus on ALE of metals and metal oxides for logic and DRAM, including process fundamentals, selectivity mechanisms, and thermal ALE processes developed at EMD Electronics.
Speaker Bio:
Martin McBriarty leads atomic layer etch development at EMD Electronics in San Jose, California.
He earned his B.S. in Materials Science & Engineering at the University of Florida in 2008 and his Ph.D. in the same field at Northwestern University in 2014. He studied at the Fritz Haber Institute as a Fulbright scholar and completed postdoctoral work at Pacific Northwest National Laboratory before joining Intermolecular (a business of Merck KGaA, Darmstadt, Germany) in 2018.
Thanks to Eurofins EAG Laboratories for providing the venue for this seminar.
======================================================================
New CMOS-Compatible Materials for Efficient Infrared Light-Absorption and Emission
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Francesca Iacopi. The title of the lecture is ‘New CMOS-Compatible Materials for Efficient Infrared Light-Absorption and Emission’
When/Where: 14th Mar, 2024, 11:30 am. In-person event (Venue: EAG Laboratories – 810 Kifer Road, Sunnyvale)
(Use corner entrance: Kifer Road / San Lucar Court. Do not enter at main entrance on Kifer Road)
Note: MUST RSVP to attend in-person
Registration: Link
Speaker: Dr. Carlos Augusto
Abstract:
Efficient photon absorption and emission require semiconductors with direct bandgaps. Si and SiGe have indirect bandgaps and the wavelength range is determined by their bulk properties. Using proprietary ab-initio modeling, Quantum Semiconductor has invented atomistically-ordered superlattices made of Group IV elements (C, Si, Ge, Sn, Pb) strained to silicon surfaces, that have direct bandgaps across the infrared spectrum, and that can be monolithically integrated with CMOS. This approach overcomes the limitations of pure silicon devices – sensing light outside the visible range of wavelengths, and light emission. Also, the photon collection process is decoupled from CMOS junction engineering, thereby allowing these devices to track Moore’s Law with each new design generation, as well as use the most advanced substrates for state-of-the-art CMOS such as fully depleted thin-film SOI. This CMOS-compatible technology platform enables innovative new products for IR image sensing, photonics, and AI.
Read more: https://quantumsemi.com/
Speaker Bio:
Carlos Augusto, Ph.D., is a co-founder and the Chief Technology Officer of Quantum Semiconductor. A prolific inventor, he is responsible for Quantum Semiconductor’s core technology. Dr. Augusto has been in the semiconductor industry for over 25 years. Previously, he was at IMEC in Leuven, Belgium where he was a member of the research staff in the Advanced Silicon Devices Group and worked on the device, process, modeling and fabrication of SiGe Vertical MOSFETs and DRAMs. After IMEC, Dr. Augusto was recruited by Rockwell Semiconductor in Newport Beach, California and moved to the United States where he was in the Advanced Process Development Group and worked on device and process integration architecture development.
Carlos has a BSc. in Physics from the Instituto Superior Técnico, Technical University of Lisbon, Portugal, M.S. in Physics of Microelectronics and Materials Science, and Ph.D. in Electrical Engineering with a specialty in device physics from the Catholic University of Leuven, Belgium. He is the author or co-author of 32 granted and 2 pending US patents, covering Advanced CMOS devices and fabrication architectures, SiGeC Photo-Diodes and CMOS pixel designs and image-sensors, Group-IV superlattices and optoelectronic devices incorporating them.
Thanks to Eurofins EAG Laboratories for providing the venue for this seminar.
======================================================================
Ferroelectronics for next generation memory and NAND storage technology
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Asif Khan. The title of the lecture is ‘Ferroelectronics for next generation memory and NAND storage technology’
When/Where: 19th Jan, 2024, 12 noon. Hybrid event (Venue: Atherton Room, Plug and Play Tech Center, 440 N Wolfe Rd, Sunnyvale, CA 94085)
Note: MUST RSVP to attend in-person
Registration: Link
If you face an issue with vtools registration send an email to hiuyung.wong at ieee.org to get the zoom link and indicate whether you are an IEEE member, IEEE EDS member, IEEE Student member
Contact: hiuyung.wong at ieee.org
Speaker: Prof. Asif Khan
Abstract:
The rise of artificial intelligent (AI)-driven marvels hinges on the unrelenting advances in digital memory and storage solutions. The exponential trajectory of improvements of dynamic random-access memory (DRAM) and NAND flash, which are the mainstays of main memory and storage, respectively, is however facing formidable challenges at the technology level.
In this talk, we will discuss the potential of the emerging ferroelectric technologies to upend the DRAM and NAND landscapes [1-3]. We will highlight how ferroelectrics can enable the transition from 2-D to 3-D in DRAM technology and facilitate vertical scaling in NAND technology to achieve the 1000-layer milestone and beyond. We will also explore how ferroelectric devices can contribute to embedded and storage class memory technologies and examine the challenges they face.
[1] Asif Islam Khan, Ali Keshavarzi, and Suman Datta. “The future of ferroelectric field-effect transistor technology.” Nature Electronics 3.10 (2020): 588-597.
[2] Dipjyoti Das, Asif Khan et al. “Experimental Demonstration and Modeling of a Ferroelectric Gate Stack with a Tunnel Dielectric Insert for NAND Applications.” Proceedings of the 2023 IEEE International Electron Devices Meeting (IEDM).
[3] Nirmal Ramaswamy et al. “NVDRAM: A 32Gb Dual Layer 3D Stacked Non-volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI Workloads.” Proceedings of the 2023 IEEE International Electron Devices Meeting (IEDM).
Speaker Bio:
Asif Khan is an Associate Professor in the School of Electrical and Computer Engineering with a courtesy appointment in the School of Materials Science and Engineering at Georgia Institute of Technology. Dr. Khan’s research focuses on ferroelectric materials and devices to address the challenges faced by the semiconductor technology due to the end of transistor miniaturization. His work led to the first experimental proof-of-concept demonstration of the ferroelecric negative capacitance, which can reduce the power dissipation in transistors. His recent interest is understanding and demonstrating the fundamental limits of memory technologies concerning their scalability, density, capacity, performance, and reliability. His group publishes research on topics that include both logic and memory technologies, as well as artificial intelligence and neuromorphic hardware. Dr Khan’s notable awards include the DARPA Young Faculty Award (2021), the NSF CAREER award (2021), the Intel Rising Star award (2020), the Qualcomm Innovation Fellowship (2012), TSMC Outstanding Student Research Award (2011) and University Gold Medal from Bangladesh University of Engineering and Technology (2011). Dr. Khan received the Class of 1934 CIOS Honor Roll award for excellence in teaching a graduate course on Quantum Computing Devices and Hardware in Fall 2020. He is presently serving as an editor at IEEE Electron Device Letters. In the past, he has also worked as an associate editor for IEEE Access, and as a technical program committee member for various conferences including IEEE International Electron Devices Meeting (IEDM) and Design Automation Conference (DAC), among others.
======================================================================
European Open Source PDK Initiative Technology – Devices – Applications
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Dr. Wladek Grabinski. The title of the lecture is ‘FOSS TCAD/EDA Tools SPICE and Verilog – A Modeling Flow’
When/Where: Refer registration link (available early Dec)
Registration:Link
If you face an issue with vtools registration send an email to hiuyung.wong at ieee.org to get the zoom link and indicate whether you are an IEEE member, IEEE EDS member, IEEE Student member
Contact: hiuyung.wong at ieee.org
Speaker: Dr. Wladek Grabinski
Abstract:
Compact/SPICE models of circuit elements (passive, active, MEMS, RF, Microwave, Photonics) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along the complete technology/design tool chain from nanascaled technology processes; thru the compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Application and use of these tools for advanced IC design (e.g. analog/RF, Microwave, Photonics applications) directly depends on the quality of the compact model implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the semiconductor device level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.
Speaker Bio:
Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETH Zürich, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPF Lausanne, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now a consultant responsible for modeling, characterization and parameter extraction of MOS transistors for the design of RF CMOS circuits. He is currently consulting on the development of next-generation compact models for the nanoscaled technology very large scale integration (VLSI) circuit simulation. His current research interests are in high-frequency characterization, compact modeling and its Verilog-A standardization as well as device numerical simulations of MOSFETs for analog/RF low power IC applications. He is an editor of the reference modeling book Transistor Level Modeling for Analog/RF IC Design, and also authored or coauthored more than 70 papers. Wladek has established ESSDERC TPC Track3: “Device and circuit compact modeling” as well as was serving as a member of the IEEE EDS Compact Modeling Technical Committee, European representative in the ITRS Modeling and Simulation Working Group; organization committees of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ. He was a Member At Large of Swiss IEEE ExCom and mentor of the EPFL IEEE Student Branch, now. Wladek is involved in activities of the MOS-AK Association and serves as a coordinating R&D manager since 1999.
======================================================================
Some efforts toward the modeling of integrated antennas
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Dr. Roberto S. Murphy. The title of the lecture is ‘Some efforts toward the modeling of integrated antennas’
When/Where: Refer registration link (available early Dec)
Registration:Link
If you face an issue with vtools registration send an email to hiuyung.wong at ieee.org to get the zoom link and indicate whether you are an IEEE member, IEEE EDS member, IEEE Student member
Contact: hiuyung.wong at ieee.org
Speaker: Dr. Roberto S. Murphy
Abstract:
With the development of faster, reliable and proven silicon based technologies, it is now possible to integrate antennas on chip (AoC), even though the semiconductor substrate is not the most convenient one for antenna applications. Nevertheless, an important number of research groups worldwide have made considerable advances in this field. Among many of the aspects being worked upon, the compact modeling of antennas outspends. The aim is to have SPICE compatible models in order to simulate the complete circuit as one, and avoid having different simulations and sets of parameters for the circuit and the antenna. In this talk, I will present some of the aspects that the group at INAOE (Puebla, Mexico)
has been tackling towards this end.
Speaker Bio:
Roberto S. Murphy-Arteaga received his B.Sc. degree in Physics from St. John’s University, Minnesota, and got his M.Sc. and Ph.D. degrees from the National Institute for Research on Astrophysics, Optics and Electronics (INAOE), in Tonantzintla, Puebla, México. He has been a researcher at INAOE since 1988. Since then, he has presented over 140 talks at scientific conferences, directed twelve Ph.D. dissertations, 20 M.Sc. and 3 B.Sc. theses, published more than 160 articles in scientific journals, conference proceedings and newspapers, and is the author of a text book on Electromagnetic Theory. His research interests are the physics, modeling and characterization of the MOS Transistor and passive components for high frequency applications, especially for CMOS wireless circuits, as well as antenna design for wireless communications. He is a member of the Mexican Academy of Sciences, of the Mexican National System of Researchers (SNI), as well as a Distinguished Lecturer of IEEE-EDS.
======================================================================
Investigating quantum speed limits with superconducting qubits
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Meenakshi Singh. The title of the lecture is ‘Investigating quantum speed limits with superconducting qubits’
When: Friday, Oct. 20, 2023 – 9am to 10am (PDT)
Where: This is an online event and attendees can participate via Zoom.
Registration:Link
If you face an issue with vtools registration send an email to hiuyung.wong at ieee.org to get the zoom link and indicate whether you are an IEEE member, IEEE EDS member, IEEE Student member
Contact: hiuyung.wong at ieee.org
Speaker: Prof. Meenakshi Singh
Abstract:
The speed at which quantum entanglement between qubits with short range interactions can be generated is limited by the Lieb-Robinson bound. Introducing longer range interactions relaxes this bound and entanglement can be generated at a faster rate. The speed limit for this has been analytically found only for a two-qubit system under the assumption of negligible single qubit gate time. We seek to demonstrate this speed limit experimentally using two superconducting transmon qubits. Moreover, we aim to measure the increase in this speed limit induced by introducing additional qubits (coupled with the first two). Since the speed up grows with additional entangled qubits, it is expected to increase as the system size increases. This has important implications for large-scale quantum computing.
Speaker Bio:
Dr. Singh is an experimental physicist with research focused on quantum thermal effects and quantum computing. She graduated from the Indian Institute of Technology with an M. S. in Physics in 2006 and received a Ph. D. in Physics from the Pennsylvania State University in 2012. Her Ph. D. thesis was focused on quantum transport in nanowires. She went on to work at Sandia National Laboratories on Quantum Computing as a post-doctoral scholar. She is currently an Associate Professor in the Department of Physics at the Colorado School of Mines. At Mines, her research projects include measurements of spin-orbit coupling in novel materials and thermal effects in superconducting hybrids. She recently received the NSF CAREER award to pursue research in phonon interactions with spin qubits in silicon quantum dots.
======================================================================
October 24-25, 2023, Quantum Computing: Devices, Cryogenic Electronics and Packaging (Link)
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is co-hosting this event.
When: Wednesday, September 20, 2023 – 3:30 pm to 5 pm (PDT)
Where: SEMI World Hdqtrs, Milpitas, CA USA
This is a hybrid event so speakers and attendees can choose to participate either in person or online
Registration Link: Here
Contact: hiuyung.wong at ieee.org
======================================================================
======================================================================
Defense Microelectronics Industrial Base
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is co-hosting this event. The title of the lecture is ‘Defense Microelectronics Industrial Base’
When: 25 Oct 2023, 06:30 PM to 08:00 PM (Eastern Time)
Where:
101 Maple Ave E, Vienna, Virginia
Building: Patrick Henry Library, Room Number: Meeting Room
If you wish to attend virtually, please register to receive the WebEx information.
Registration Link: Here
Contact: hiuyung.wong at ieee.org
Speaker: Dr. Clifford Lau of Institute for Defense Analyses
Abstract:
Semiconductor microelectronic chips are critical components in defense C4ISR and weapon systems. Department of Defense (DoD) needs to have an assured supply of advanced microcroelectronic chips, in peacetime and wartime. Since DoD itself normally does not make the chips, DoD depends on the semiconductor industry to produce the needed chips. DoD uses a variety of chips, many are commercial-off-the-shelf (COTS) and some are classified and defense-unique chips. The semiconductor industry, although originally created by DoD, for several decades has gradually moved off-shore, including fabrication, testing, and packaging. The U.S. market share of global semiconductor manufacturing capacity has fallen from about 38% in 1990 to 12% in 2020. TSMC in Taiwan is the world’s largest semiconductor chip manufacturer, supplying 92% of worlds sub-nanometer advanced chips. To bring semiconductor manufacturing back to the U.S., Congress passed the CHIPS and Science Act to reshore semiconductor manufacturing to the U.S. The CHIPS Act authorizes more than $200B, and immediately appropriates $53.7B, in federal funding to promote domestic semiconductor manufacturing production, DoD allocated $2B as a part of the CHIPS Act. DoD’s Microelectronics Commons initiative selected eight regional innovations hubs that include a large number of members in the industrial base. The objective of these hubs, called “lab to fab”, is to speed up the transition of microelectronics from research to prototyping to production, and is focused on strengthening the defense microelectronics industrial base.
Speaker Bio:
Dr. Clifford Lau is a research staff member at the Institute for Defense Analyses (IDA) performing studies and analyses to support the Office of Secretary of Defense and other defense and federal agencies. Prior to joining IDA, he spent a long career as scientific officer and program director in the Office of Naval Research (ONR) managing various basic science research programs in electronics, computers, and signal processing. He also spent six years as senior scientist at DDR&E managing the MURI, DURIP, and other defense S&T programs. He received his Ph.D. from UC Santa Barbara in 1978, M.S. from UC Berkeley in 1967, and B.S. from UC Berkeley in 1966, all in electrical engineering and computer science. He has published 56 papers and edited 7 books on neural networks and fault tolerant computing. In his 50 years of IEEE membership, he has served in various capacities, including serving as President of the IEEE Neural Networks Council (now the Computational Intelligence Society) in 1999-2000, President of the IEEE Nanotechnology Council in 2004, Vice President in Circuits and Systems Society in 1996-1997. He was a member of IEEE TAB in 1999-2000 and 2004. He served as associate editors and guest editors for various IEEE Transactions, including TNN, TAC, TCAS, and Proceedings. He was on the Editorial Board of the Proceedings of the IEEE in 1988-1996. He was General Chair for several major IEEE conferences, including IEEE-NANO and IJCNN. He was chair of IEEE-USA R&D Policy Committee in 2004-2006. In 2007 he was the IEEE-USA Vice President for Technology Policy. He is a Life Fellow of the IEEE.
======================================================================
CHIPS: An Unprecedented Opportunity What This Program Means
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is co-hosting this event. The title of the lecture is ‘CHIPS: An Unprecedented Opportunity What This Program Means’
When: Wednesday, September 20, 2023 – 3:30 pm to 5 pm (PDT)
Where:
101 Maple Ave E, Vienna, Virginia
Building: Patrick Henry Library, Room Number: Meeting Room
If you wish to attend virtually, please register to receive the WebEx information.
Registration Link: Here
Contact: hiuyung.wong at ieee.org
Speaker: Dr. Michael Fritze
Abstract:
Dr. Fritze will give his independent perspectives on what the CHIPS (Creating Helpful Incentives to Produce Semiconductors) Program means for the US particularly for the microelectronics community. He will cover the motivations behind this historic semiconductor investment and articulate the planned support level for each particular area. This includes the Department of Commerce Incentives and R&D efforts and the Department of Defense Microelectronics Commons. Particular attention will be paid to the R&D parts of this legislation. He will review the goals of this legislation in strengthening the US domestic microelectronics supply chain and R&D infrastructure. Dr. Fritze will also discuss some of the key challenges of this major US Government investment.
Speaker Bio:
Dr. Fritze is an independent technology consultant. He is a Senior Fellow and former Vice President at the Potomac Institute for Policy Studies. He is also a Consultant at Trusted Strategic Solutions. His interests include USG trusted microelectronics access strategies, support of needed legacy technologies, DOD innovation policy and outreach to Industry and strengthening the US Microelectronics Industrial Base. He has supported a variety of USG organizations primarily in the DoD on these issues.He is also a member of the Industrial Advisory Committee supporting the NIST CHIPS R&D efforts.
Dr. Fritze was the Director of the Disruptive Electronics Division at the USC Information Sciences Institute (2010-2015). He also held a Research Professor appointment in the USC Ming Hsieh Department of Electrical Engineering (Electrophysics). His research interests at ISI included Trusted Electronics, CMOS Reliability & Robustness, Low power 3DIC enabled electronics and Rad-hard electronics. He was a Program Manager at the DARPA Microsystems Technology Office (MTO) from 2006-2010. While at DARPA, Dr. Fritze was responsible for Programs in the areas of 3D Integrated Circuits (3DIC), Steep-Subthreshold-slope Transistors (STEEP), Radiation Hardening by Design (RHBD), Carbon Electronics for RF Applications (CERA), Silicon-based RF (TEAM), Ultra-low power Digital (ESE), Highly regular designs (GRATE) and Leading-edge foundry access (LEAP).
Prior to joining DARPA, Dr. Fritze was a staff member from 1995-2006 at MIT Lincoln Laboratory in Lexington, Massachusetts, where he worked on fully-depleted silicon on insulator (FDSOI) technology, silicon-based integrated optics and development and resolution-enhanced optical lithography.
Dr. Fritze received a Ph.D. in Physics from Brown University in 1994, working in the area of compound semiconductor quantum well physics. He received a B.S. in Physics in 1984 from Lehigh University. Dr. Fritze is an elected member of Tau Beta Pi and Sigma Xi. He is a recipient of the Office of the Secretary of Defense Medal for Exceptional Public Service awarded in 2010. He is a Senior Member of the IEEE and is active on the GOMAC Conference Program Committee as well as the NDIA Electronics Division Policy Group. Dr. Fritze has published over 75 papers and articles in professional journals and holds several U.S. Patents.
======================================================================
August 14-16, 2023, 5th IEEE International Flexible Electronics Technology Conference (IFETC) 2023 (Link)
======================================================================
======================================================================
What Are 2D Materials Good For?
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Eric Pop. The title of the lecture is ‘What Are 2D Materials Good For?’
When: Friday, July 28, 2023 – 12 Noon to 1 pm (PDT)
Where: This is an online event and attendees can participate via Zoom.
Registration Link: Here
Contact: hiuyung.wong at ieee.org
Speaker: Prof. Eric Pop
Abstract:
This talk will present my (biased!) perspective of what two-dimensional (2D) materials could be good for. For example, they could be good for applications where their ultrathin nature gives them distinct advantages, such as flexible electronics [1] or light-weight solar cells [2]. They may not be good where conventional materials work sufficiently well, like transistors thicker than a few nanometers. I will focus on 2D materials for 3D heterogeneous integration of electronics, which presents major advantages for energy-efficient computing [3]. Here, 2D materials could be monolayer transistors with ultralow leakage [4] (due to larger band gaps than silicon), used to access high-density memory [5]. Recent results from our group [6,7] and others [8] have shown monolayer transistors with good performance, which cannot be achieved with sub-nanometer thin conventional semiconductors, and the 2D performance could be further boosted by strain [9]. I will also describe some unconventional applications, using 2D materials as thermal insulators [10], heat spreaders [11], and thermal transistors [12]. These could enable control of heat in “thermal circuits” analogous with electrical circuits. Combined, these studies reveal fundamental limits and some unusual applications of 2D materials, which take advantage of their unique properties.
Refs: [1] A. Daus et al., Nat. Elec. 4, 495 (2021). [2] K. Nassiri Nazif, et al., Nat. Comm. 12, 7034 (2021). [3] M. Aly et al., Computer 48, 24 (2015). [4] C. Bailey et al., EMC (2019). [5] A. Khan et al. Science 373, 1243 (2021). [6] C. English et al., IEDM, Dec 2016. [7] C. McClellan et al. ACS Nano 15, 1587 (2021). [8] S. Das et al., Nat. Elec. 4, 786 (2021). [9] I. Datye et al., Nano Lett. 22, 8052 (2022). [10] S. Vaziri et al., Science Adv. 5, eaax1325 (2019). [11] C. Koroglu & E. Pop, IEEE Elec. Dev. Lett. 44, 496 (2023). [12] M. Chen et al., 2D Mater. 8, 035055 (2021).
.
Speaker Bio:
Eric Pop is the Pease-Ye Professor of Electrical Engineering (EE) and Materials Science & Engineering (by courtesy) at Stanford, where he leads the SystemX Heterogeneous Integration focus area and the EE Culture, Equity, and Inclusion committee. His research interests include nanoelectronics, data storage, and energy. Before Stanford, he spent several years on the faculty of UIUC, and in industry at Intel and IBM. He received his PhD in EE from Stanford (2005) and three degrees from MIT in EE and Physics. His awards include the PECASE from the White House, and Young Investigator Awards from the Navy, Air Force, NSF CAREER, and DARPA. He is an APS and IEEE Fellow, an Editor of 2D Materials, and a Clarivate Highly Cited Researcher. In his spare time he enjoys snowboarding and tennis, and in a past life he was a college radio DJ at KZSU 90.1. More information about the Pop Lab is available at http://poplab.stanford.edu and on Twitter @profericpop..
======================================================================
======================================================================
EDS DL Event: Artificial Intelligence and Brain Biofields Quantum Computing
The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting an EDS Distinguished Lecturer Dr. Adam Skorek. The titled of the lecture is ‘Artificial Intelligence and Brain Biofields Quantum Computing.
When: Friday, May 19, 2023 – 12 Noon to 1 pm (PDT)
Where: This is an online event and attendees can participate via Zoom.
Registration Link: Here
Contact: hiuyung.wong at ieee.org
Speaker: Prof. Adam Skorek (EDS Distinguished Lecturer)
Abstract:
Artificial intelligence (AI) is present in electrical, electronics, and computer engineering for years. In particular, the biofields defined as electromagnetics and thermal fields in living matter are naturally related to AI studies and applications, including brain analysis with numerical modeling and simulations. Brain functionalities inspire all developments in AI from theoretical investigations to machine learning, humanoids robots, Digital Twins (DT), and brains interface devices implementation. The brain biofields’ interactions with external excitations such as 5G/6G telecommunications devices, transcranial magnetic stimulation, and even other brains biofields are currently explored more than ever before. The computation demand in modeling and simulation is still growing and it is particularly high in both AI and brain biofields applications. Hopefully, the High-Performance Computing (HPC) and High-Performance Quantum Computing (HPQC) infrastructures become more easily accessible and offer researchers some new opportunities based on the open and shared resources including not only computing facilities with quantum units but also knowledge with currently observed openings in the field of intellectual property issues. A presentation from a worldwide perspective of some modern research works with their results applications is completed by the lecturer’s experiences and guidelines for the future. Some practical examples and instructions for researchers, engineers, and students are presented, stimulating the audience to various scientific as well R&D activities in those so promising areas.
Speaker Bio:
Prof. Adam Waldemar Skorek (M’87, SM’90, F’09, LF’23) completed Bachelor and Master of Electrical Engineering Program at Białystok University of Technology (Poland) receiving both Master and Engineer degrees in 1980. Participant of the Electrical Engineering Faculty Doctoral Studies, he received a Doctor of Technical Sciences degree in Electrical Engineering at Warsaw University of Technology (Poland) in 1983. From 1983 to 1987 he was a Visiting Lecturer at the Institute of Telecommunications in Oran (Algeria). In 1987, he joined the University of Quebec at Trois-Rivières (UQTR), Canada, where currently, he is a Full Professor and Director of the UQTR’s Electro-Thermal Management Laboratory which succeeded both the Nano-Heat Laboratory and Industrial Electro-Heat Laboratory, all founded and directed by himself since 1989. He is conducting electrical engineering courses for bachelor, master, and Ph.D. students. His research works were granted by NSERC, CFI, FRQNT, MITACS, and Industry. He was made contributions to the numerical analysis of electro-thermal and biofields phenomena exploring and applying various techniques to electrical apparatus, electronic devices, and living organisms. His publications and communications record include works on High-Performance Computing, Artificial Intelligence, Digital Twins (DT) and Quantum Computing applications, in electro-thermal and biofields analysis. A number of those publications are available in IEEE Xplore. The IEEE Life Fellow, as well as Fellow of the Engineering Institute of Canada, Prof. Adam W. Skorek is a Member of the Engineering Academy in Poland and recipient of the 2021 IEEE Industry Applications Society Distinguished Service Award.
======================================================================
======================================================================
IEEE SCV-SF EDS Mini Colloquium (March 24, 2023)
The Electron Devices Society Santa Clara Valley/San Francisco Chapter with the San Jose State University IEEE student chapter is hosting a mini-colloquium celebrating the 75th anniversary of the invention of the transistor. In this mini-colloquium, we are inviting 3 speakers to each give talks on topics ranging from traditional/planar transistors and advanced transistors to analog technology.
When: Friday, March 24, 2023 – 12 Noon to 2 pm (PST)
Where: This is a hybrid event so speakers and attendees can choose to participate either in person at SJSU Engineering building Rm. ENGR 376 or online via Zoom (link will be sent after registration).
Registration Link: Here
Contact: hiuyung.wong at ieee.org
Title: Sustaining the AI Revolution: Transistor Scaling and Beyond
Speaker: Prof. Tsu-Jae King Liu
Abstract:
Advancements in semiconductor integrated circuit (IC) “chip” technology over the past 60+ years have enabled exponential growth in chip functionality with exponential reduction in cost per transistor, resulting in the proliferation of information and communication devices and systems, with revolutionary impact on society; today cloud computing, big data and artificial intelligence are driving the digital transformation of all industries. In this talk I will discuss three dimensions of IC technology advancement – transistor scaling, new computing architectures and new computing paradigms – to usher in the Age of Ambient Intelligence.
Speaker Bio:
Tsu-Jae King Liu earned her B.S., M.S. and Ph.D. degrees in electrical engineering at Stanford University in 1984, 1986 and 1994, respectively. From 1992 to 1996, she was member of research staff at the Xerox Palo Alto Research Center (PARC). In 1996, she joined the faculty of the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley, where she is now Dean of the College of Engineering.
Liu is internationally known in academia and industry for her innovations in semiconductor devices and technology, and is highly regarded for her achievements as an instructor, mentor and administrator. She is a fellow of the Institute of Electrical and Electronics Engineers (IEEE), an elected member of the U.S. National Academy of Engineering, a fellow of the U.S. National Academy of Inventors, and Director of Intel Corporation and of Maxlinear, Inc. Her awards and honors include the Intel Outstanding Researcher in Nanotechnology Award, the IEEE Aldert van der Ziel Award for distinguished educational and research contributions to the field of electronic devices and materials, the IEEE Electron Devices Society Education Award, and the Defense Advanced Research Projects Agency (DARPA) Significant Technical Achievement Award for her role in the development of the FinFET, an advanced transistor design used in all high-end computer chips today.
=x=x=x=
Title: Semiconductors in Extreme Environments
Speaker: Prof. Debbie G. Senesky
Abstract:
Wide bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN) and, diamond are well known for their inherent resilience to high-temperature and radiation-rich environments. This makes them attractive electronic platforms for use in space exploration and other extreme-environment applications (e.g., combustion, downhole, hypersonic aircraft). Gallium nitride (GaN) electronics have operated at temperatures as high as 1000°C making it a viable platform for robust space-grade (“tiny-but-tough”) electronics and nano-satellites. Even with this major technological breakthrough, there are still challenges in making GaN in low-cost formats with low defect density for proliferation in “beyond silicon” applications. New communities are adopting this electronic platform for a multitude of emerging device applications including the following: sensing, energy harvesting, actuation, and communication. In this talk, we will review and discuss the benefits of GaN’s two-dimensional electron gas (2DEG) over silicon’s p-n junction for space exploration applications (e.g., radiation-hardened, temperature-tolerant Venus probes). In addition, we will discuss the use of prolonged microgravity environments on the International Space Station (ISS) and commercial stations for future manufacturing of semiconductors for the benefit of life on Earth.
Speaker Bio:
Debbie G. Senesky is an Associate Professor at Stanford University in the Aeronautics and Astronautics Department and by courtesy, the Electrical Engineering Department. In addition, she is the Principal Investigator of the EXtreme Environment Microsystems Laboratory (XLab). Her research interests include the extreme-environment sensors, high-temperature electronics for Venus exploration, and nanomaterials synthesis within prolonged microgravity. She received the B.S. degree (2001) in mechanical engineering from the University of Southern California. She received the M.S. degree (2004) and Ph.D. degree (2007) in mechanical engineering from the University of California, Berkeley. She is currently serves as the Site Director for nano@stanford, as well as co-editor for the IEEE Journal of Microelectromechanical Systems (JMEMS) and Sensors (journal). In recognition of her work, she is a recipient of the Emerging Leader Abie Award from AnitaB.org, NASA Early Faculty Career Award, and Alfred P. Sloan Foundation Ph.D. Fellowship Award. More information about Prof. Senesky can be found at xlab.stanford.edu or on Instagram: @astrodebs.
=x=x=x=
Title: The Evolution of Analog Technology
Speaker: Lou N Hutter
Abstract:
Despite the major advancements made in semiconductor technology, the world remains a very analog place. Consequently, analog and power management integrated circuits are ubiquitous in almost every electronic system built today. Analog technology has made significant strides in the past 50+ years, migrating from low-density bipolar-based technologies and SSI products to highly scaled CMOS-based nodes and LSI and VLSI products today. The wide diversity of analog applications has driven a wide diversity of process technologies. This talk will discuss the evolution of analog technology from the 1970s to today and beyond, highlighting the many design constraints that have led to the diverse technology portfolio and rich component sets used today.
Speaker Bio:
Lou is a veteran of the semiconductor industry. He spent 29 years at Texas Instruments Inc., until retiring in 2007, as Director of TI’s Mixed-Signal Technology Development organization where he was responsible for worldwide analog, power, RF SiGe, and mixed-signal technology development, process delivery kits, production ramps, and transfers that supported every business unit in the company. He was elected a TI Fellow in 1995 based on his technical accomplishments and their revenue impact. In 2008, he joined Dongbu HiTek, in Seoul, S. Korea, as Senior Executive Vice President and General Manager of the newly created Analog Foundry Business Unit, where he was responsible for technology development, design enablement, IP development, and sales and marketing. During his tenure there, he increased revenues 4X, added many and significant new customers, and established Dongbu HiTek as a leading analog/power management foundry in the industry. Since 2012, he has been Principal of Lou Hutter Consulting LLC, advising foundries, IDMs, fabless companies, and material suppliers in the areas of analog and power technology, design infrastructure, organizational management, and business development. Lou has 47 U.S. patents, has published over 35 journal articles, has co-authored 1 book entitled Silicon Analog Components, now in its 2nd edition, and other book chapters. He has an MSEE from the Massachusetts Institute of Technology, and resides in Dallas, Texas.
======================================================================
Title: Gallium Nitride MMIC Power Amplifiers
for High Throughput Satellite (HTS) Applications (co-sponsored event with MTT-SCV)
Speaker: Jim Sowers
Wednesday, March 15, 2023
Registration Link: Here
Abstract:
There is a need for Solid State Power Amplifiers (SSPA’s) to be used in High Throughput Satellites (HTS) for commercial applications. Specifically when the amount of information passed through the transponders, i.e. capacity, is determined mainly by the quantity of beams the satellite can generate. This application is well suited for SSPA’s over the conventional TWTA solution as they are smaller and lighter weight enabling a simplification of HTS payload architectures, higher density physical integration, and the ability to support active array transmit solutions all of which increases the quantity of beams and thus capacity. More specifically, Gallium Nitride (GaN) Power Amplifiers (PA’s) have shown the ability to generate high RF output power levels with small size and high efficiency thereby enabling step function improvement in capacity. This paper will describe a 20GHz fully space qualified GaN PA module developed for KaBand commercial satellite downlinks. The design techniques, test results, and screening regimen required to meet the demanding performance and reliability requirements will be given. The result is a 20GHz module with >55dB of gain, >10W of Pout, >30% peak PAE, and NPR >15dB. To the authors knowledge this is the best fully space-qualified module performance at this frequency published to date.
Speaker Bio:
Jim has 40+ years of experience designing, developing, and manufacturing of RF, microwave, and millimeter-wave microelectronic components for satellite payloads as well as communication and radar systems for commercial and military use.
He is currently Payload Technical Partner for Unit Design Engieering and a Distinguished Engineer at Maxar Space Infrastructure. His responsibilities have encompassed the development of space-qualified, RF active, payload components from C-Band through V-Band including GaN Power Amplifiers, LNA’s, Receivers, Linearized Channel Amplifiers, Local Oscillators and MMICs. Additional responsibilities included Payload Manager for large Ku and Ka Band programs. Joining SS/L in June 1999, he was the Section Manager for Repeater Subsystems Electrical Engineering.
Preceding employent at SS/L, Mr. Sowers was with Lockheed Martin/Martin Marietta/GE Aerospace and was responsible for the research, design, and development of microwave and millimeter-wave MMICs and components for advanced radar and communications systems.
After graduating from Cornell University with a BSEE Jim joined Varian Associates where he was responsible for the research, design, and development of InP Gunn and IMPATT devices and circuits at V and W Bands. Receiving his Master of Science degree from Stanford University he subsequently took a position with Harris Microwave Semiconductor to develop RF/Microwave amplifiers for the military market.
Jim is a Life Senior Member of the IEEE, and has served on the Technical Program and Steering Committee of several IEEE conferences and is a past chair of the IEEE MTT Society -Santa Clara Valley Chapter. Additionally, he maintains an Adjunct Professor position at Santa Clara University.
===================================================================
Title: Atomistic Quantum Transport Modelling for Emergent 2D Material-based Device
Speaker: Dr. Youseung Lee
Friday, January 27, 2023 – 12:00PM – 1:00PM PDT
Registration Link: Here
Abstract:
Over the years, most of the manufactured electronic devices started to have at least one dimension in the nanometer scale. Concurrently, the non-equilibrium Green’s function (NEGF) framework has been broadly democratized to investigate quantum transport effects inside those devices. The latter framework has also proven its importance to correctly capture the underlining physics for the nano-scale devices. This talk will then discuss the latest development of atomistic quantum transport modelling for various emerging 2D materials-based devices. The first part of the talk will show an ab-initio approach that correctly captures the scattering mechanisms present in 2D FETs, combining the linearized Boltzmann Transport Equation (LBTE) and the NEGF formalism. Atomistic defect-variability study for 2D monolayer MoS2 FETs via many body defect-level corrections will also be presented. The second part will show the application of the ab-initio modeling framework to simulate Majorana transport, paving the way for topological qubits based on 2D nanoribbons. Atomistic modelling of van der Waals charge qubit manipulations and measurements in 2D materials will also be covered.
Speaker Bio:
Youseung Lee is a Post-doctoral Researcher at Nano-TCAD group of Integrated Systems Laboratory, ETH Zürich, Switzerland. He started his professional career as a TCAD engineer in Samsung Electronics Semiconductor Research Center, Korea in 2010 after he obtained MSc from KAIST. At Samsung, he worked on the development of 20, 14, and 10 nm logic technology nodes through TCAD process/device simulations. After the industrial career, he joined IM2NP-CNRS (Institut Matériaux Microélectronique Nanosciences de Provence) National Laboratory, France for PhD. Currently his main research focuses on the development of physics models dedicated to nano-electronic devices, along three main pillars: (A) computationally efficient quantum transport methods, (B) many body physics modelling, and (C) atomistic modelling for quantum computing devices hosting qubits.
===================================================================
Co-sponsored Event with SF Bay Area PELS Chapter
Title: Wide Bandgap Semiconductors: Opportunities and Challenges for Improved Modeling and Characterization Methods in Power Electronic Applications
Speaker: Prof. Raghav Khanna
Thursday, January 26, 2023 at 6:30PM – 8:00PM PDT
Abstract:
Wide bandgap semiconductor devices based on gallium nitride (GaN) and silicon carbide (SiC) offer myriads of advantages over traditional silicon (Si)-based devices for applications in power electronics. These advantages include, among others, faster switching capabilities, allowing for reduced filtering components within converter topologies, thus leading to improved power density. Despite their many advantages, several challenges related to technological readiness level have hindered the widespread adoption of these devices. At the device-physics level, for example, the theoretical high voltage capability of GaN has yet to be commercially realized. At the device-circuits level, the fast-switching capability of SiC, though generally a beneficial attribute, has led to undesirable injected harmonic content into power electronic converters, leading to detrimental circuit-behavior. For these reasons, advanced modeling, and characterization methods for both GaN and SiC are needed, so that these devices can realize their full performance entitlement.
This talk will present a broad array of modeling and characterization methodologies for GaN and SiC semiconductors. Device physics simulations using finite element modeling techniques will be presented, demonstrating the high voltage capability of vertical GaN diodes. It will be shown how these types of models can lead to the design and fabrication of future high voltage and reliable vertical GaN devices. Analytical physics-based models of GaN diodes, based on first principles, will also be presented. For these types of models, tradeoffs between model-fidelity and convergence-time in circuit-simulations will be discussed. Behavioral models of SiC MOSFETs, based on mathematical curve-fitted equations, will then be presented. These models will demonstrate the need to capture the frequency-dependence of the device’s parasitic per-terminal junction capacitances, as well as that of the parasitic package inductances, in order to construct a comprehensive empirically validated high-fidelity circuit-simulation. New strategies that can enable the development of hybrid-physics and -behavioral models will be presented, in a manner that offers utility to both device fabrication engineers, as well as application-circuit designers. For the various types of models presented, the importance of the interplay and refinement between simulation and empirical validation will be emphasized. This talk will conclude with characterization techniques and opportunities for wide bandgap semiconductors in space. The work presented in this talk lends itself well to developing strategies for multilevel integrated modeling infrastructures of next generation GaN and SiC devices, and to aid in the design, fabrication, and implementation of future high-voltage and reliable wide and ultrawide bandgap semiconductors.
Speaker Bio:
Raghav Khanna received the B.S. degree, M.S. degree, and Ph.D. degree in electrical engineering from the University of Pittsburgh, Pittsburgh, PA, USA in 2007, 2010, and 2014, respectively. Raghav has worked for several industries including Lockheed Martin (Philadelphia, PA), PPG Industries (Pittsburgh, PA) and HRL Laboratories (Malibu CA). At HRL, he was directly involved with the development of GaN based battery chargers for electric vehicles. In 2015, he joined the electrical engineering and computer science department at The University of Toledo. He is currently an Associate Professor and holds the position of Leidich Family Endowed Professor in Power and Energy Systems. His research interests are in characterization and modeling of wide bandgap semiconductors for applications in next generation power electronics, including; renewable energy, electric vehicles, aerospace and maritime systems, and in low power consumer electronics. He is also conducting extensive research on control strategies for integration of distributed energy resources. He recently received grants from the U.S. Department of Defense, U.S. Department of Energy, and NASA Jet Propulsion Laboratory to further develop his research activities.
===================================================================
IEEE-EDS September Seminar (Webex only)
Title: Design and Modelling Challenges for Very Large-Scale Integrated Quantum Processors in Foundry CMOS Technologies
Speaker: Sorin P. Voinigescu
Friday, November 18th, 2022 at noon – 1PM PDT
Webex link will be distributed to the registrant via email.
Organizer contact: Hiu Yung Wong (hiuyung.wong at sjsu.edu)
Abstract:
This presentation will discuss the main challenges in the physical implementation, design, hierarchical modelling and simulation of the scalable qubit array and of the cryogenic control and readout electronics for future Quantum Processors with millions of qubits manufactured in commercial FDSOI and FinFET foundry technologies. Impact of process manufacturing rules restrictions and process variation on qubit design and modelling, circuit heat dissipation and layout miniaturization to fit the qubit array pitch, qubit-to-qubit crosstalk, and the need for atomistic, classical, and behavioural qubit simulation and modelling will be covered in detail.
Speaker Bio:
Sorin P. Voinigescu is a Professor in the Electrical and Computer Engineering Department at the University of Toronto where he holds the Stanley Ho Chair in Microelectronics and is the Director of the VLSI Research Group. He is an IEEE Fellow and an expert on millimeter-wave and 100+Gb/s integrated circuits and atomic-scale semiconductor device technologies. He obtained his PhD degree in Electrical and Computer Engineering from the University of Toronto in 1994 and his M.Sc. Degree in Electronics and Telecommunications from the Politechnical Institute of Bucharest in 1984.
———————————————————————-
Title: The LLNL Quantum Design and Integration Testbed
Speaker: Dr. Yaniv Jacob Rosen
Friday, September 2, 2022 at noon – 1PM PDT
Webex link will be distributed to the registrant via email.
Organizer contact: Hiu Yung Wong (hiuyung.wong at sjsu.edu)
Abstract:
Quantum science and technology is a focal point of research at LLNL. To that end we are developing QuDIT, a quantum testbed that allows us to explore different methods of implementing quantum computing and sensing. In this presentation we will introduce the basics of quantum computing and how they achieve a speedup in computation. We will explore LLNL’s implementation which uses the higher levels of the quantum elements to increase the computational space. Despite adding computational complexity, using Qudits instead of Qubits simplifies the hardware and can improve performance for certain calculations. We will show example simulation pulses developed using optimal control techniques designed to solve quantum systems, and discuss the sources of noise and decoherence that affect our system. This presentation will attempt to give a broad overview of the RF engineering, the material science, and the classical computer science that goes into developing the LLNL testbed.
Speaker Bio:
Dr. Yaniv is the deputy group leader of the Quantum Coherent Device Physics group. He works on noise in superconducting devices with an emphasis on two-level-system dielectric loss. Yaniv graduated with a B.A. in physics and applied mathematics from the University of California (UC), Berkeley in 2006. He received his Ph.D. in condensed matter physics under Ivan Schuller at UC San Diego in 2013, where he studied thin-film superconductivity under the influence of nano-magnetic dots. From there he engaged in postdoctoral study at the Laboratory for Physical Sciences with Kevin Osborn, studying two-level systems in dielectrics. In 2016, he joined the Lawrence Livermore team where he helped bring online the LLNL Quantum design and Integration Testbed.
Title: Memristive Neuromorphic Computing Beyond Moore’s Law
Speaker: Prof. Sung-Mo “Steve” Kang, UC Santa Cruz
Friday, November 12, 2021 at noon – 1PM PDT
Webex link will be distributed to the registrant via email.
Organizer contact: Jin-Woo Han (jin-woo.han at nasa.gov)
Abstract:
Neuromorphic computing is pursued to overcome the limitations of von Neumann architecture and Moore’s law. Harnessing brain-inspired properties such as in-memory computing, spike-based encoding, and adaptation has demonstrably shown to bolster energy-delay efficiency by a few orders of magnitude classes of computation. The use of functional building blocks in integrated circuits that exhibit characteristics like the biological building blocks of the central nervous system is expected to enable circuits to mimic tasks associated with human cognition and sensory perception. Thus, a variety of approaches has been used to design electronic neurons that generate spiking signals and to implement synaptic interconnects. The memristor was introduced by Leon Chua in 1971 as a circuit element that is as fundamental as R, L, and C. The notion of the memristor was generalized by Chua and Kang in 1976. The research and development of memristor circuits and systems were propelled by the nanoscale memristors fabricated by Williams et al. in 2008. Since then, a myriad of applications has been developed for memristors in storage-class memory, sensing, logic operations and memcomputing. Recently, memristors have become available through commercial fabrication processes and are commercially used in non-volatile resistive random-access memories (RRAM). Memristor technologies have ushered in new approaches for emulating both biological neurons and synapses. Synaptic plasticity has been demonstrated in memristors by using spike trains to increase (potentiate) or decrease (depress) the memristor’s conductance. In this talk, we will discuss the roles of memristors in designing new building blocks for memristive neural networks for hardware acceleration. How to design new memristive neurons and synapses for neuromorphic computation will be discussed in view of integration packing density, power consumption, and physical layout of neuronal networks. It is projected that at the 3.5 nm memristor technology node, memristive neurons and synapses in mimicry of human brain can be densely integrated in a 2400 〖cm〗^2 of surface area with a total power consumption in the ballpark of 20W.
Speaker Bio:
Sung-Mo “Steve” Kang is a Distinguished Chair Professor of the Jack Baskin School of Engineering, UC Santa Cruz, and Chancellor Emeritus of UC Merced and President Emeritus of KAIST. He returned to academia in 1985 from industry to join the faculty of the University of Illinois at Urbana-Champaign. Until then, he had led the development of world’s premier CMOS 32-bit VLSI microprocessor chipsets for telecommunication and computing applications as a technical supervisor of AT&T Bell laboratories, Murray Hill, NJ. From 1995 to 2000, he served as Department Head of ECE at the University of Illinois at Urbana-Champaign and became a Dean of Engineering at UC Santa Cruz. He has received honors, including the Silicon Valley Engineering Hall of Fame induction, Alexander von Humboldt Senior US Scientists Award, IEEE Millennium Medal, IEEE Mac Van Valkenburg Circuits and Systems (CAS) Society Award, IEEE CAS Technical Excellence Award, the US Semiconductor Research Corporation (SRC) Technical Excellence Award, IEEE Graduate Teaching Technical Field Award, IEEE CAS John Choma Education Award, Chang-Lin Tien Education Leadership Award, and distinguished alumnus awards from UC Berkeley, The University at Buffalo, Fairleigh Dickinson University, and Yonsei University. He received his B.S. degree from Fairleigh Dickinson University, Teaneck, New Jersey in 1970, M.S. degree from the State University of New York at Buffalo in 1972, and Ph.D. degree from UC Berkeley in 1975. He holds 16 U.S. patents, published over 500 papers, and 10 books. Dr. Kang is a Fellow of the IEEE, the Association for Computing Machinery (ACM), and the American Association for the Advancement of Science (AAAS). He is a member of Korean Academy of Science and Technology and a foreign member of National Academy of Engineering, Korea. His research interest includes modeling and simulation of semiconductor devices, memristors and memristive systems, low-power VLSI circuit design, nano-bioelectronic circuits, and neuromorphic computing.
Title: TCAD/SPICE-Augmented Machine Learning for Defect and Variation Study
Speaker: Dr. Hiu Yung Wong, San Jose State University
Friday, October 15, 2021 at noon – 1PM PDT
Webex link will be distributed to the registrant via email.
Organizer contact: John Choi (wonhochoi at micron.com)
Abstract:
In semiconductor technology development, it is desirable to pinpoint the source of defect or variation through electrical measurements, which are non-destructive and have much higher throughput than the traditional failure analysis. This can be achieved through machine learning which is a powerful tool for correlating the electrical characteristics to the nature of the defect/variation. However, a good machine is only possible with enough well-controlled training data, which is difficult to obtain experimentally. TCAD and SPICE simulations which are well-calibrated to experimental data are proposed to generate the training data.
In this talk, we will first demonstrate the use of TCAD to generate data to train machines to deduce the epitaxial layer thickness of Si p-i-n diodes and the workfunction and operating temperature variation of Ga2O3 Schottky Barrier Diodes, based solely on the measured electrical characteristics. We will emphasize the use of minimal domain expertise to obviate the difficulties in feature extraction. We will also demonstrate the techniques that are important to make the TCAD-trained machine applicable to predicting experimental data. SPICE-augmented ML will be demonstrated for detecting contact resistance degradation in inverters. Finally, we will discuss the use of TCAD-augmented machines to help reverse engineering and understand novel devices.
Speaker Bio:
Hiu Yung Wong is an Assistant Professor in the EE department, San Jose State University. He received his Ph.D. degree in Electrical Engineering and Computer Science from the University of California, Berkeley in 2006. From 2006 to 2009, he worked as a Technology Integration Engineer in Spansion. From 2009 to 2018, he was a TCAD Senior Staff Application Engineer in Synopsys, during which he received Synopsys Excellence Award in 2010. In 2021, he received the NSF CAREER award and the Newnan Brothers Award for Faculty Excellence.
His research interests include the applications of machine learning in simulation and manufacturing, cryogenic electronics, quantum computing, reliability simulations, wide bandgap devices (such as GaN, SiC, Ga2O3, and diamond) simulations, novel semiconductor devices design, and Design Technology Co-Optimization (DTCO). His work has produced 80 papers and 10 issued patents.
IEEE-EDS April Seminar Series (Webex only)
Title: An Addiction to Low Cost Per Memory Bit – How to Recognize it and What to Do About it
Speaker: Dr. Andy Walker, Spin Memory inc.
Friday, April 23, 2021 at noon – 1PM PDT
Abstract:
The phenomenal rise in the amounts of data has put great pressure on the semiconductor industry to provide low cost memory solutions. The result is a constant drive to lower the cost per bit of DRAM, SRAM and NAND Flash. In addition, AI requires intense store and recall between processor and memory. In the rush to provide low cost solutions, other attributes have been treated as expendable as an acceptable cost of doing business. Several examples come to mind: short product lifetimes because of limited NAND Flash endurance; data insecurity because of DRAM Rowhammer; poor energy efficiency because of the need to bring growing amounts of data from DRAM into the processor chip due to SRAM area inefficiencies. All such “negative externalities” have a cost that is not included in the product cost but affects society in terms of wasted energy and resources. This talk looks into their origins and consequences and is a call to action for a more comprehensive understanding of what cost per bit really means.
Speaker Bio:
Andy Walker has been working in silicon technology since 1985. After a BSc in physics from Dundee University in Scotland he joined Philips Research Laboratory in Eindhoven, The Netherlands. His PhD from the Technical University of Eindhoven arose from his research work at Philips. In 1994 he came to Silicon Valley and worked at various companies including Cypress, Matrix and Spin Memory. He also founded Schiltron Corporation to develop new forms of monolithic memories. He has been fortunate in being able to work in many interesting areas of silicon devices and process technology including MOS device physics, nonvolatile memories, ESD and Latch-up, TFTs and MRAM.
IEEE-EDS January Seminar Series (Webex only)
Title: Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects
Speaker: Prof. Shimeng Yu, Georgia Institute of Technology
Friday, January 15, 2021 at noon – 1PM PDT
Abstract:
Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in the deep learning accelerator. In this presentation, first I will present our DNN+NeuroSim benchmark framework that is interfaced with Tensorflow/PyTorch to evaluate different device technologies for state-of-the-art DNN models. We will discuss about the pros and cons of various non-volatile memory candidates and the most important device specifications for inference/training, respectively. Second, I will present our RRAM-CIM prototype chips that are integrated with CMOS peripheral circuitry and its performance. Furthermore, we will show our experimental characterizations of the multilevel RRAM’s variability and reliability and their impact on DNN inference accuracy. To overcome the challenges of the RRAM-CIM prototypes we identified, we propose monolithic 3D integration with back-end-of-line (BEOL) transistors as a potential solution.
Speaker Bio:
Shimeng Yu is an associate professor of electrical and computer engineering at the Georgia Institute of Technology. He received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University. Prof. Yu’s research interests are nanoelectronic devices and circuits for energy-efficient computing systems. His expertise is on the emerging non-volatile memories (e.g., RRAM, ferroelectrics) for different applications such as deep learning accelerator, neuromorphic computing, monolithic 3D integration, and hardware security. Among Prof. Yu’s honors, he was a recipient of the NSF Faculty Early CAREER Award in 2016, the IEEE Electron Devices Society (EDS) Early Career Award in 2017, the ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, the Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, and the ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award in 2020, etc. Prof. Yu is active in professional services. He served or is serving many premier conferences as technical program committee, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology, etc. He is a senior member of the IEEE..
************************************************************************************
IEEE-EDS October Seminar Series (Webex only)
Title: Coupled Oscillator based Computing: Using Nature to Solve Difficult Problems
Speaker: Prof. Chris H. Kim, University of Minnesota
Friday, October 30, 2020 at 11AM – noon PDT
Abstract:
In this talk, I will introduce a first-of-its kind quantum-inspired coupled oscillator based compute engine implemented in a standard 65nm technology targeted for NP-hard or NP-complete problems such as max-cut, graph coloring, traveling salesman, and pattern recognition. The NP-hard problem is first mapped to the coupling weights while the solution is represented by the phases of the individual oscillators, which are read out using on-chip phase sampling circuits. Our hardware exploits the natural tendency of a network of coupled oscillator to settle to the ground state, which offers significant performance and power advantages compared to traditional digital approaches.
Speaker Bio:
Chris H. Kim received his B.S. and M.S. degrees from Seoul National University and a Ph.D. degree from Purdue University. He is currently a professor at the University of Minnesota. Prof. Kim is the recipient of the University of Minnesota Taylor Award for Distinguished Research, SRC Technical Excellence Award, Council of Graduate Students Outstanding Faculty Award, NSF CAREER Award, Mcknight Foundation Land-Grant Professorship, 3M Non-Tenured Faculty Award, DAC/ISSCC Student Design Contest Award, IBM Faculty Partnership Award, IEEE Circuits and Systems Society Outstanding Young Author Award, the ICCAD Ten Year Retrospective Most Influential Paper Award, ISLPED Low Power Design Contest Award (4 times), and ISLPED Best Paper Award (2 times). His group has expertise in digital, mixed-signal, and memory IC design, with special emphasis on circuit reliability, hardware security, memory circuits, radiation effects, time-based circuits, beyond-CMOS technologies, and machine learning hardware design. He is an IEEE fellow.
************************************************************************************
Title: Memory Errors in Production Systems – Insights from the Field
Speaker: Dr. Sudhanva Gurumurthi, Principal Member of Technical Staff, AMD
Friday, August 28, 2020 at 12PM – 1PM PDT
Abstract:
Memory reliability is important for the correct operation of computing systems. While technology scaling as paved the way for improvements in the capacity and energy-efficiency of memory, the reliability aspects of such scaling must be well characterized and addressed in the design of computer hardware. AMD has collected and analyzed memory reliability data from several production systems running in data centers. This data spans several generations of DRAM technologies, as well as SRAM. This talk will first explain how bit-cell reliability can impact on the design and use of computing hardware and highlight the importance of studying memory faults from commercial hardware in the field. The talk will then present memory reliability data and insights from AMD’s field studies and discuss their implications from the viewpoint architecting resilient systems.
Speaker Bio:
Sudhanva Gurumurthi is a Principal Member of the Technical Staff at AMD, where he leads advanced development in Reliability, Availability, and Serviceability (RAS). He used to be an Associate Professor with tenure in the Computer Science Department at the University of Virginia. Sudhanva is a recipient of the NSF CAREER Award, a Google Focused Research Award, two Google Faculty Research Awards, and other NSF and industry awards. He is a Senior Member of the IEEE and the ACM.
************************************************************************************
IEEE-EDS July Distinguished Lecture: Differentiated Fully Depleted SOI (FDSOI) Technology for Highly Efficient and Integrated mmWave Wireless Connectivity Solution (Webex Only)
Speaker: Dr. Anirban Bandyopadhyay, Director, Strategic Marketing and Business Analytics, GLOBALFOUNDRIES, Inc., Santa Clara, CA
Friday, July 24, 2020 at 12PM – 1PM PDT
Abstract:
The emergence of enhanced mobile broadband (eMBB) connectivity based on mmWave 5G and the emerging prospect of broadband internet to using non-terrestrial mmwave backhaul using low earth orbit (LEO) satellite generated huge interest in the entire telecommunication ecosystem. While mmwave allows huge bandwidth of channels to enable enhanced broadband, it also poses a lot of technical challenges in terms of coverage, generating enough transmitted power efficiently particularly in the uplink, system cost & scaling and long term reliability of the hardware system particularly for infrastructure including Satellite born systems. Current talk will focus on how Silicon technologies based on differentiated fully depleted SOI (FDSOI) can address the above challenges by enabling a highly efficient and integrated radio without compromising on the mmWave performance and reliability. Talk will highlight the technology Figures of Merits (FOMs) for a mmwave phased array system and how a differentiated FDSOI technology platform compares with other silicon technologies in terms of devices and circuits.
Speaker Bio:
Dr. Anirban Bandyopadhyay is the Director, Strategic Marketing and Business Analytics within the Mobility & Wireless Infrastructure Business Unit of GLOBALFOUNDRIES, USA. His work is currently focused on hardware architecture & technology evaluations for emerging RF and mmWave applications. Prior to joining GLOBALFOUNDRIES, he was with IBM Microelectronics, New York and with Intel, California where he worked on different areas like RF Design Enablement, Silicon Photonics, signal integrity in RF & Mixed signal SOC’s. Dr. Bandyopadhyay did his PhD in Electrical Engineering from Tata Institute of Fundamental Research, India and Post-Doctoral research at Nortel, Canada and at Oregon State University, USA. He represents Global Foundries in different industry consortia on RF/mmWave applications and is a Distinguished Lecturer of IEEE Electron Devices Society.
************************************************************************************
IEEE-EDS June Seminar: (Ultra-) Wide-Bandgap Devices: Reshaping the Power Electronics Landscape (Webex Only)
Speaker: Dr. Yuhao Zhang, Assistant Professor, Center for Power Electronics Systems, Virginia Tech
Friday, June 12, 2020 at 12PM – 1PM PDT
View Presentation
Abstract:
Power electronics is the application of solid-state electronics for the control and processing of electrical energy. It is used ubiquitously in consumer electronics, electric vehicles, data centers, renewable energy systems, and smart grid. The power semiconductor device, as the cornerstone technology in power electronics, is key to improving the efficiency, cost and form factor of power electronic systems.
Recently, the power electronics landscape has been significantly reshaped with the production and application of power devices based on wide-bandgap (WBG) semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC). Besides advancing the performance of traditional power systems, WBG devices have also enabled many emerging applications that are beyond the realm of silicon (Si) as well as changed the manufacturing paradigm of power electronics. On the horizon is the power devices based on ultra-wide-bandgap (UWBG) materials, which promises superior performance over GaN and SiC and is at the relatively early stage of research development.
This talk will provide a comprehensive overview of major WBG and UWBG power device technologies, spanning materials, devices, reliability and applications. Some research projects in the PI’s group in collaboration with industry will also be introduced.
Speaker Bio:
Dr. Yuhao Zhang is an assistant professor in the Center for Power Electronics Systems (CPES) at Virginia Tech. Before joining CPES, he worked as a postdoctoral associate at Massachusetts Institute of Technology (MIT) from 2017 to 2018. He received his Ph. D. and S. M., both in electrical engineering from MIT in 2017 and 2013, respectively. Prior to joining MIT, he received his B. S. in physics from Peking University in 2011 with the highest honor. He received the MIT Microsystems Technology Laboratories Doctoral Dissertation Award in Spring 2017, for his impactful work on vertical GaN power devices.
His research interest is at the intersection of power electronics, micro/nano-electronic devices and advanced semiconductor materials. His group is currently working on the development of novel WBG and UWBG power devices, reliability and robustness of emerging power devices, and ultra-wide bandgap power semiconductors.
Center for Power Electronics Systems (CPES) (https://cpes.vt.edu/) at Virginia Tech is one of the largest university research center in power electronics. For the past two decades, CPES has a worldwide reputation for its research advances, its work with industry to improve the entire field, and its many talented graduates. The CPES industry consortium comprises over 80 member companies engaged with CPES to stay abreast of technological developments in power electronics.
************************************************************************************
IEEE-EDS March Seminar: Wide Bandgap Devices Enabling High Power and High Frequency Electronics (Webex Only)
Speaker: Professor Srabanti Chowdhury, Stanford University
Friday, March 13, 2020 at 11:45AM – 1PM
Abstract:
We live in extremely exciting times, often identified as the age of the fourth industrial revolution. With electrification at every level, we are witnessing the most significant transformation of transportation since the internal combustion engine. Renewable energy is now a reality. IoT with the ever-expanding need for sensors and low power electronics is changing our lives dramatically. Robotics and autonomous vehicles are upon us. Both new and existing applications are demanding physical electronics solutions with new materials, devices and heterogeneous integration to drive these innovations to their full potential.
Wide-bandgap (WBG) semiconductors present a pathway to enable much of these electronics with higher efficiency and newer functionalities. Semiconductor devices with higher power density have unprecedented value in both power and high frequency electronics. Reducing conversion losses is not only critical for minimizing consumption of limited resources, it simultaneously enables new compact and reduced weight solutions, the basis for a new industry offering increased power conversion performance at reduced system cost. Equally importantly, GaN has opened the door to other ultra-wide bandgap materials such as Diamond, Aluminum Nitride and Gallium Oxide.
Speaker Bio:
Srabanti Chowdhury (George and Ida Mary Hoover faculty fellow, Gabilan fellow) is an associate professor of Electrical Engineering (EE) at Stanford. She received her masters and PhD in Electrical engineering from UCSB in 2008 and 2010 respectively. Her research focuses on wideband gap (WBG) materials and device engineering for energy efficient and compact system architecture for power electronics, and RF applications. Besides Gallium Nitride, her group is exploring Diamond for various electronic applications. She received the DARPA Young Faculty Award, NSF CAREER and AFOSR Young Investigator Program (YIP) in 2015. In 2016 she received the Young Scientist award at the International Symposium on Compound Semiconductors (ISCS). She became a senior member of IEEE in 2017, and NAE Frontiers of Engineering Alumni in 2019. She has been named as a Sloan Research Fellow in 2020 in Physics for her research contribution.
Among her various synergistic activities, she serves as the member of two committees under IEEE Electron Device Society (Compound Semiconductor Devices & Circuits Committee Members and Power Devices and ICs Committee). She has served the IEEE International Electron Devices Meeting (IEDM) technical subcommittee on Power Devices & Compound Semiconductor and High-Speed Devices (PC) sub-committee in 2016 and 2017. She was the PC subcommittee chair for IEDM-2018 and continues to serve the IEDM executive committee. Her work has produced over 80 journal papers, 100 conference presentations, and 20 issued patents.
************************************************************************************
Heterogeneous Integration Roadmap Symposium and Annual Meeting [more]
— intro to HIR v1.0, overviews, integration, working groups, 15-year projections …
— Thurs (at Samsung in SJ) & Friday (at SEMI in Milpitas), February 20-21, 2020
— $50 for IEEE/ASME members; $60 for non-members; $25 for retired/students (includes two lunches)
Speakers: from Intel, Boeing, Fraunhofer, NASA, Infineon, Google, Advantest, ASE, ITRI, SEMI, UI-UC, U-Md, UCLA, more
Who should attend: Engineers and managers in the materials, devices, photonics, packaging, supply chain, assembly and test disciplines; Open to the General Public
Summary: Heterogeneous Integration will be the key technology direction going forward, for device and subsystem integration. It is the “low hanging fruit” for initiating a new era of technological and scientific advances. The 2019 HIR edition was released October 2019. This Annual Meeting kicks off the revision work for the 2020 HIR Edition.
Day 1: Progress toward Heterogeneous Integration: Implementation of HIR v1.0; Work on v2.0 — Presentations from all 22 HIR Technical Working Group chairs; panels — How to Download and Use the Roadmap
Keynote Speakers: Pradeep Dubey, Intel Sr Fellow; Hong Liu, Distinguished Engineer & Senior Director, Google Technical Infrastructure
4 Sessions: — Heterogeneous Integration for High Performance; — Heterogeneous Integration for Consumer & Industrial Applications; — Heterogeneous Integration for High-Performance Computing; — Heterogeneous Integration for Special Applications
Day 2: TWG Breakout Sessions for HIR v2.0 — TWG Caucuses & Cross-TWG meetings
For a full information, please see the website: www.cpmt.org/scv/?p=999
************************************************************************************
EDS Distinguished Lecturer Mini-colloquium
We have a mini-colloquium presented in partnership with the IEEE EDS DL Program and the SJSU Electrical Engineering Department.
Friday, December 6, 2019 1PM-3PM – No cost to attend
San Jose State University Charles W. Davidson College of Engineering, Room E285/287
Distinguished Lecturers and Topics
Current progress and future perspectives in polymer solar cells, Lluís F. Marsal, Professor, University of Rovira i Virgili, Spain
Physics and modeling of organic thin film transistors, Benjamin Iñiguez, Professor, University of Rovira i Virgili, Spain
Silicon technologies for 5G, Anirban Bandyopadhyay, Director, GLOBALFOUNDRIES, Inc.
——————————————-
Current progress and future perspectives in polymer solar cells
Polymer solar cells are considered as a promising renewable energy source because of their
light-weight, high transparency, possibility of fabrication in large areas and inexpensive solar
energy production. These solar cells are based in the junction of two different organic
semiconducting materials, one donor and one acceptor. The most efficient devices to date are
the bulk heterojunction cells, obtained from a mixture of the donor and acceptor materials,
which provides an enormous interfacial surface.
In the last years, advances in polymer-based organic solar cells have been possible due to
different approaches such as design of new structures and synthesis of new materials such as
small molecule and polymers with low band-gaps, control of the nanoscale morphology, new
interfacial transport layers, variation of the ratio of the donor/acceptor in the bulk
heterojunction, application of thermal or solvent annealing process, among others [1-4]. As
a result, recently, power conversion efficiencies over 16% are obtained. However, there are
still some problems to solve such as the stability, more efficient architectures and degradation
process of the polymeric solar cells. In this lecture, we will present the perspectives and
recent advances made in polymer solar cells, design and synthesis of new polymers and in
particular the active layer morphology, interfacial layers and stability. We will also discuss
the basic device operation and various parameters limiting their efficiency and their possible
solutions.
Prof. Lluis F. Marsal is Distinguished Professor and full
professor at the University Rovira i Virgili, Spain. Ph.D. from
the University Politecnica de Cataluña, Spain, 1997.
Postdoctoral researcher at the ECE, University of Waterloo,
Canada (1998-1999).
In 2012, he received the URV’s RQR Award for the high quality
in research and in 2014, he received the UniSA Distinguished
Researcher Award, and the 2014 ICREA Academia Award
from the Generalitat of Catalunya. Since 2019, he is the Chair
of the Subcommittee for Regions/Chapters (SRC) – Regions
8, IEEE- EDS. He was the Chair of Spain Chapter of the IEEE-EDS (2013-2018). He
is a senior member of the IEEE and a member of the Distinguished Lecturer program
of the EDS. He has co-authored more than 200 publications in international refereed
journals, 2 books, 5 book chapters and 3 patents. His current research interests
focus on organic and hybrid solar cells and nanostructured materials for
optoelectronic devices and low–cost technologies based on micro- and nanoporous
materials for biosensing and bio-applications.
************************************************************************************
IEEE EDS August Seminar
Title: Doping profile control via oxygen-insertion silicon channel and its benefit of device performance
Speaker: Hideki Takeuchi, Atomera Inc.
Tuesday, August 13, 2019 at 6:00PM
Interstitial trapping by OI (oxygen-inserted) silicon channel results in blocking of boron and phosphorus TED (transient enhanced diffusion) as well as retention of channel boron profiles during the gate oxidation process. The OI layers are also beneficial for achieving USJ (ultra-shallow junctions) with low sheet resistance (Rsh) formed by high-dose implantation and rapid thermal annealing because they reduce dopant diffusion away from the surface and can provide for higher levels of active dopant concentration. The enhanced doping profile control capability is applicable to punch-through stop of advanced CMOS devices and its benefits to 28 nm planar CMOS and bulk FinFET devices projected by TCAD are discussed.
Speaker Biography
Hideki Takeuchi is Director of MST Integration at Atomera Inc. He received M.E. degree at University of Tokyo in 1990. From 1997 to 2005, he worked as research staff in Semiconductor Device group at UC-Berkeley and was involved in various research activities such as fabrication and characterization of proto-type FinFET devices, HKMG material and processing, non-volatile memories, RF-MEMS, and so forth. He has been with Atomera Inc. (formerly, Mears Technologies Inc.) since 2008, and is currently in charge of process integration of the OI silicon technology (aka MSTTM).
************************************************************************************
************************************************************************************
IEEE EDS July Seminar
Title: Printed Electronics for In-Space Manufacturing
Speaker: Jin-Woo Han, NASA Ames Research Center
Tuesday, July 23, 2019 at 6:00PM
Abstract
In this talk, the on-demand printed electronics activities as a part of NASA In-Space Manufacturing program will be presented. An overview of our emerging printed devices including gas sensors, memory devices, energy storage devices, triboelectric nanogenerators, and others will be provided. In addition to printing the devices and integration of the devices into systems, tool development is receiving attention, rightfully so in order to meet the anticipated demands of the internet of things (IoT).
Speaker Biography
Jin-Woo Han is a Scientist at the Center for Nanotechnology, NASA Ames Research Center, Moffett Field, California, USA. He has received the NASA Ames Honor Award, the IEEE Electron Device Society Early Career Award, Outstanding Engineering Achievement Merit Award from Engineers’ Council, the 2015 Mike Sargeant Award from the Institute of Engineering and Technology, IET, UK), IEEE Nanotechnology Council Early Career Award and the Presidential Early Career Award for Scientists and Engineers (PECASE) Award in 2016. He has published over 140 articles in peer-reviewed journals and given 40 invited talks on his subject areas in national and international conferences and universities. He is also active in the IEEE Electron Devices Society (EDS) serving in various technical committees including IEDM.
************************************************************************************
************************************************************************************
IEEE EDS Distinguished Lecturer Series
Title: Nitrided and Fluorinated Graphene for the Applications on High Mobility Graphene Transistor, Memory and Chemical Sensors
Speaker: Prof. Chao-Sung Lai, Chang Gung University
Thursday, May 30, 2019 at 6:00PM
Abstract
A novel graphene based insulator, fluorographene, is firstly applied as gate dielectric in a field effect transistor. To identify the dielectric quality, dielectric constant, breakdown electric field and thermal stability are investigated. In this talk, the scalable and one-step fabrication of single atomic-layer transistors is demonstrated by the selective fluorination of graphene using a low-damage CF4 plasma treatment, where the generated F-radicals preferentially fluorinated the graphene at low temperature (<200 °C) while defect formation was suppressed by screening out the effect of ion damage. The fluorographe was also used as decoupling for graphene as its substrate and mobility was improved much. Graphene nanodiscs (GNDs), functionalized using NH3 plasma, as charge trapping sites (CTSs) for non-volatile memory applications have been investigated. The fabrication process relies on the patterning of Au nanoparticles (Au-NPs), whose thicknesses are tuned to adjust the GND density and size upon etching. A GND density as high as 8 × 10¹¹ cm⁻² and a diameter of approximately 20 nm are achieved. The functionalization of GNDs by NH3 plasma creates NH⁺ functional groups that act as CTSs, as observed by Raman and Fourier transform infrared spectroscopy. This inherently enhances the density of CTSs in the GNDs, as a result, the charge loss is less than 10% for a 10-year data retention testing, making this low-temperature process suitable for low-cost non-volatile memory applications on flexible substrates. Moreover, the pH, pNa ion sensing properties of graphene based ion-sensor by nickel end contact modification were demonstrated. The pH and pNa sensitivities were around 36.5mV/pH and 15.3mV/pNa, respectively, for pristine graphene. For Ni end-contact modified graphene, sensitivities are changed to 41mV/pH and no pNa sensitivity.
Speaker Biography
Chao-Sung Lai received the B. S. and ph. D. degrees from National Chiao Tung University, Hsinchu, Taiwan, in 1991 and 1996, respectively. In 1996, he joined National Nano Device Laboratories, Hsinchu, where was engaged in the research of silicon-on-insulator devices. He then, in 1997, joined Chang Gung University as a faculty in the department of electronic engineering. He has been engaged in the research of the characterization and reliability of MOSFETs, Flash memory and transistor based biosensors. From 2001 to 2002, he visited the Department of Electrical Engineering, University of California, Berkeley, for visiting research on fin-shaped FETs. Since 2007 to 2013, he had been the Chairman of the Department of Electronic Engineering and the Director of the Biosensor Group of the Biomedical Research Center, Chang Gung University, for the research-related bio-transistor application on ions, proteins, DNA, and biomarker analysis. From 2012 till now, he is the Dean of Engineering College of Chang Gung University. He holds 11 U.S. patents and 60 Taiwan patents, and he is the author of more than 350 SCI journal and conference papers, 25 international invited talks, and 2 book chapters. He is the Leading Guest Editor of the SCI journals, including Microelectronics Reliability (2010), Nano-Scaled Research Letters (2011), and Solid-State Electronics (2012). He won Lam Research Award in 1997 and distinguished award from Electron Devices and Materials Association in 2011 and Association of Chemical Sensing Technology in 2015. From 2016, he was elected as the president of Association of Chemical Sensing Technology. He has served as organizing committees for several international conferences, including general chair (IEEE-INEC 2011), (IEEE-ISNE 2015) and international advisory committee (IEEE-ISNE 2016) and (IEEE-EDSSC 2017).
************************************************************************************
Saturday, May 11, 2019 at 10:30AM
Title: Simulations of Nanoscaled Transistors Including Self-Heating Effects: From Coupled Phonon/Carrier Boltzmann Equations Approach to Coupled Drift-Diffusion/Heat Equations Model
Speaker: Dr. Anh-Tuan Pham, Samsung Semiconductor, Inc
Abstract
Recently, some improvements on the fabrication technology make strained SiGe become a promising candidate among novel channel materials for boosting the performance of the existing strained Si pFinFET architecture. However, self-heating (SH) effects in such SiGe devices are significantly pronounced due to low thermal conductivity of SiGe alloy. The consequent SH effects may seriously hamper the performance and reliability of device. In this talk, self-heating effects on transport of holes in SiGe pFinFETs are demonstrated. The coupled system of Boltzmann Transport Equation (BTE) for holes and phonons is solved self-consistently. For transport of holes, the multi subband BTE is solved for 1D hole gas system, where the subband structure is computed from the 2D k · p Schroedinger Equation /3D Poisson equation solution. For transport of phonons, the BTE for 4 phonon modes (LA, TA, LO, TO) in 3D k–space is solved based on first order spherical harmonic expansion (SHE) method. This study demonstrates the strong dependence of pMOS SH on Ge content. As Ge mole fraction increases above 0.2, alloy scattering hampers the thermal conductivity by more than one order of magnitude. Combined with boundary scattering and smaller band-gap of SiGe, this effect may pose some alarms on next generation pMOS devices. A simplified approach based on coupled drift-diffusion/heat equations is also employed. Comprehensive comparison of the 2 approaches is shown. Hierarchical scheme combined both approaches is proposed.
Speaker Biography
Anh-Tuan Pham received the MSc and PhD from University of Bremen, and Technical University of Braunschweig, Germany in 2004 and 2010, respectively. In 2010, he joined the physical device simulation group @ IMEC in Leuven, Belgium as a post-doctoral researcher working on the junctionless nanowire transistor simulation project. From 2011 to 2013, he joined Synopsys Inc. in Mountain View, CA and engaged in the development of the commercial SBand tool. In 2013, he joined Samsung Semiconductor Inc. in San Jose, CA and engaged in device research and development of device simulation tool. He is the author and co-author of 50+ publications including 2 book chapters.
************************************************************************************
************************************************************************************
April 9, 2019
Using new physics of nonlinear electronics for analog computing
Speaker: Dr. Suhas Kumar, HP Lab
Abstract
There is growing interest for nonlinear electronic behaviors that may enable analog computing such as brain-like neuromorphic computing, which cannot be efficiently achieved using any traditional transistor-based circuits. Nonlinear electronic components, such as memristors and neuristors, which can emulate synapses and neurons, are enabled by device physics that are barely understood. This talk will summarize some new materials physics that have enabled new device behaviors. And the talk will also highlight how the new device behaviors can enable certain analog neural network hardware for NP-hard combinatorial optimization, which cannot be implemented with any practical efficiency using traditional digital electronics.
************************************************************************************
************************************************************************************
March 5, 2019
“Spintronics-Perspectives and Challenges”
Speaker: Prof. Brajesh Kumar Kaushik, IIT
Abstract
Conventional CMOS technology has reached to the brink of its scaling limits and poses significant challenges for the development of next generation high-speed ultra-low power cost-effective memory and processing devices. The failure of Moore’s law on the technology roadmap has enforced the research community to explore alternative technology solutions to mitigate the problems. In the post-CMOS era, spintronics shall emerge as a potentially viable interdisciplinary field with credible technological perspectives. Spintronic exploits an electron’s spin orientation and its associated magnetic moment as a state variable instead of a conventionally used charge in CMOS technology. In general, the spintronic devices are layered structure of ferromagnetic materials and provide the nonvolatile storage options and manipulations of logic states. Spin transfer torque (STT) and spin orbit torque (SOT) devices using magnetic tunnel junctions (MTJs) have become strong contenders for the nonvolatile embedded memory architectures with the capability of implementing the concepts of “logic-in-memory” and “material-device-circuit co-design.” The spin torque devices offer the features of “universal memory” i.e., high speed, nonvolatility, high density, and low power, high endurance, CMOS process compatibility. Apart from the basic spin torque devices, the field of spintronics encloses all spin logic (ASL) devices, domain wall (DW) based devices, spin diodes, and spin FETs. The material and device level roadmaps for the field of spintronics suggest that the research work is at the infant stage and still require different elemental spin device developments with the understanding of associated underlying physics. In addition, the accurate models for the spintronic devices imitating the effect of stochastic behaviour and PVT variations need to be explored. Spintronics based architectures are being considered for computing applications such as bio-inspired computing and quantum computing. These spintronics based novel computing approaches find applications in image processing and provides efficient solution to the complex computing problems.
************************************************************************************
************************************************************************************
January 22, 2019
“Novel Technologies for Artificial Intelligence: Prospects and Challenges”
Speaker: Dr. Stefano Ambrogio, IBM Almaden
Abstract
Recently, Artificial Intelligence (AI), exploiting both bio-inspired algorithms, such as Spike-Timing-Dependent-Plasticity (STDP), or back-propagation algorithms, as in Deep Neural Networks (DNNs), are able to perform accurate classification of large amounts of data. However, to further proceed in the development of AI, novel hardware technologies supporting fast calculation should be developed. Recently, many algorithms have been efficiently mapped into arrays of Non-Volatile Memories, such as Phase-Change Memory (PCM) or Resistive Memory (RRAM) [1,2].
In this presentation, we provide a summary of recent progress in hardware acceleration of AI algorithms, such as the training of Fully Connected (FC) DNNs based on large arrays of PCMs. In such schemes, weights are encoded in the conductances of resistive devices, with orders of magnitude estimated increase in speed and energy efficiency with respect to current state of the art based on CPUs and GPUs [2].
In addition to speed and power consumption, the desired chip for FC DNNs training should also provide equivalent accuracy to software training. We recently provided a novel weight scheme based on PCM and CMOS circuitry able to obtain software-equivalent training accuracy on MNIST and other small and medium size datasets. Results were obtained with a mixed hardware-software experiment where CMOS circuitry was accurately simulated and PCM behavior was measured from real device arrays [3].
After this, we provide some design guidelines for the implementation of a multicore chip able to perform training of DNNs. This is obtained with many NVM arrays connected through a routing circuitry able to efficiently distribute internal signals, external inputs such as images and labels and, finally, providing the trained weights to the output [4].
************************************************************************************
************************************************************************************
December 1, 2018
“Improving the IEEE: Issues, Ideas, Best Practices”
Moderator: Dr. Renuka Jindal, Director, IEEE Division I
Abstract
This will be an event “for listening to” engineers and managers in Silicon Valley who have ideas for improving the IEEE, or have issues they’d like to raise. With input and grass-roots suggestions for improving the IEEE, I intend to provide actionable feedback at the IEEE TAB and BOD level. Your input will be critical in shaping the future of the IEEE and will need your active support to make this a reality.
If you wish to bring specific thoughts about IEEE changes, improvements and growth, be prepared to present them to the group for, say, 5 minutes, for discussion and enhancement. The meeting secretary will take notes, along with any handouts you provide, and ask for others who would like to be further involved with your specific suggestion. Renuka will receive your inputs and the summary, and is taking steps to allow him to gather world-wide input on these specific ideas that can inform and support the issues that are raised by our SV community of entrepreneurs.
Speaker Biography
Dr. Renuka Jindal’s technical focus has been on research and teaching in the theory and practice of random processes applicable to a wide variety of phenomena in electronic and photonic devices and circuits, lightwave and wireless communications and biological systems. He was with Bell Labs at Murray Hill, Princeton and Whippany, NJ as a distinguished member of technical staff for 22 years, bridging both technical and administrative roles. Highlights include his pioneering work in developing a physical understanding of noise in MOS devices with few hundred nanometers regime channel lengths and ultra-low noise amplification of fiber-optic signals. Until recently, he has served as Professor of Electrical and Computer Engineering, University of Louisiana at Lafayette.
As a 41 year veteran of IEEE with a dual career in industry and academia, Dr. Jindal rose through the ranks as Editor, Editor-in-Chief, VP of Publications, and as EDS president in 2010-2011, and now serves as Director of IEEE Division I, sitting on the IEEE Board. As EDS president he formulated the vision and mission of EDS, enhancing member benefits and launching a plethora of initiatives reversing the decline in EDS membership. He brought together 6 societies and 1 council to launch the highly successful IEEE Journal of Photovoltaics, mushrooming IEEE’s share in the PV space. He Launched the EDS webinar series serving the practicing engineer, now considered a best practice in IEEE. And he Launched the 1st EDS OPEN ACCESS Journal J-EDS. He is also a recipient of the IEEE 3rd Millennium medal.
************************************************************************************
************************************************************************************
November 30, 2018
“Materials, Devices, and Modeling of Advanced Semiconductor Devices – An IEEE EDS Distinguished Lecturer Double-Header”
Moderator: Dr. Renuka Jindal, Director, IEEE Division I
Talk 1: Are Extended Defects a Show Stopper for Future III-V CMOS Technologies, Cor Claeys, KU Leuven
The progress in epitaxial growth techniques resulted in intensive research on the potential use of non-Si based substrates, enabling the fabrication of Ge (p-channel), III-V (n-channel) or hybrid Ge/III-V devices on a Si substrate. These high mobility materials are also implemented in TFET and nanowire structures. Heterogenous integration of Ge and III-V technologies on a silicon platform enables to fabricate System-on-Chip applications and has potential for Internet-of-Things (IoT) applications. The aspect-ratio-trapping (ART) heteroepitaxy technique is successfully applied for the fabrication of non-planar devices like for Gate-All Around structures, FinFETs and TFETs. Due to the lattice mismatch between Si and the device layer (Ge or III-V), the challenge is to suppress or minimize the formation of
misfit and threading dislocations.
First a review is given of some of the present-day state-of-the art III-V devices processed on a Si platform reported in the literature, before addressing defect engineering aspects for III-V processing on a Si-platform from both a structural and electrical performance perspective. The identification of the extended defects will be illustrated by some case studies based on Deep Level transient Spectroscopy (DLTS) analysis and low frequency noise spectroscopy. Information on the basic defect parameters can be used as input for TCAD simulation of the electrical device performance, enabling a further optimization of the materials’ growth and
process conditions. The optimal goal is to determine for real devices the tolerable defect levels without penalizing their performance.
Cor Claeys is Professor at the KU Leuven (Belgium) since 1990. He was with imec, Leuven, Belgium from 1984 till 2016. His main interests are semiconductor technology, device physics, low frequency noise phenomena, radiation effects and defect engineering. He co-edited books on “Low Temperature Electronics” and “Germanium-Based Technologies: From Materials to Devices” and wrote monographs on “Radiation Effects in Advanced Semiconductor Materials and Devices”, “Fundamental and Technological Aspects of Extended Defects in Germanium” and “Random Telegraph Signals in Semiconductor Devices” and “Metals in Silicon- and Germanium-Based Technologies: Origin, Characterization, Control and Electrical Impact”. Two books are translated in Chinese. He (co)authored 14 book chapters, over 1100 conference presentations and more than 1300 technical papers. He is editor/co-editor of 60 Conference Proceedings. Prof. Claeys is a Fellow of the Electrochemical Society and of IEEE. He was Founder of the IEEE Electron Devices Benelux Chapter, Chair of the IEEE Benelux Section, elected Board of Governors Member and EDS Vice President for Chapters and Regions. He was EDS President in 2008-2009 and Division Director on the IEEE Board of Directors in 2012-2013. He is a recipient of the IEEE Third Millennium Medal and received the IEEE EDS Distinguished Service Award. Within the Electrochemical Society, he was Chair of the Electronics & Photonics Division (2001-2003) . In 2004, he received the Electronics & Photonics Division Award. In 2016 he received the Semi China Special Recognition Award for outstanding involvement in the China Semiconductor Technology International Conference (CSTIC).
***
Talk 2: Modeling and Simulation of FinFET and Nanosheet Transistors for Advanced Technology Nodes, Yogesh Chauhan, IIT Kanpur
Continued scaling of transistors has forced us to scale the channel thickness of the device to have strong electrostatic control and get rid of the short channel effects. The reduced channel thickness results in the confinement of charge carriers and larger quantization effect. In addition to the scaling, alternative channel materials having better transport properties are also being explored to boost the device performance. The promising options for channel materials in post Si era are Ge, SiGe, III-V and 2D layered semiconductors. The III-V semiconductor materials have lower effective mass and as a consequence lower density of states (DOS). The lower DOS introduces a new capacitance component in gate capacitance in addition to the existing charge centroid and gate oxide capacitance and is called as quantum capacitance. Scaling has also resulted in channel lengths of modern and upcoming devices to be comparable to the mean scattering lengths of the semiconductor material. This causes some of the charge carriers to travel from the source to the drain without any significant scattering. Therefore, the generic principles governing the drift-diffusive framework, i.e. (i) the concept of mobility, and (ii) local field dependent velocity, are no longer valid. This quasi-ballistic transport results in significant deviation from the device behaviour predicted by traditional drift diffusive models. Since different carriers experience different amounts of scattering, modeling such devices is not only interesting but also challenging. In this talk, I will discuss the physics and modelling of different quantum effects and transport in extremely scaled transistors with different channel materials.
Yogesh Singh Chauhan is an associate professor at Indian Institute of Technology Kanpur (IITK), India. He was with Semiconductor Research & Development
Center at IBM Bangalore during 2007 – 2010; Tokyo Institute of Technology in 2010; University of California Berkeley during 2010-2012; and ST Microelectronics during 2003-2004. He is the developer of industry standard BSIM-BULK (formerly BSIM6) model for bulk MOSFETs and ASM-HEMT model for GaN HEMTs. His group is also involved in developing compact models for FinFET, Nanosheet/Gate-All-Around FET, FDSOI transistors, Negative Capacitance FETs and 2D FETs.
He is the Editor of IEEE Transactions on Electron Devices and Distinguished Lecturer of the IEEE Electron Devices Society. He is the member of IEEE-EDS Compact Modeling Committee and fellow of Indian National Young Academy of Science (INYAS). He is the founding chairperson of IEEE Electron Devices Society U.P. chapter and Vice-chairperson of IEEE U.P. section. He has published more than 200 papers in international journals and conferences. He received Ramanujan fellowship in 2012, IBM faculty award in 2013 and P. K. Kelkar fellowship in 2015, CNR Rao faculty award and Humboldt fellowship in 2018. His research interests are characterization, modeling, and simulation of semiconductor devices. He has served in the technical program committees of IEDM, SISPAD, ESSDERC, EDTM, and VLSI Design conferences.
************************************************************************************
************************************************************************************
October 9, 2018
“Connecting Atomic Level Material Analysis to Transistor Scale Modeling for FinFET and Nanowire Design”
Speaker: Dr. Victor Moroz, Fellow, Synopsys
Abstract
At 5nm design rules, atomic scale effects kick in on several levels: the bandstructures of Si and SiGe fins deviate from bulk properties, impacting transistor performance by about 10%. Further scaling makes transistor behavior even more sensitive to atomic scale changes in critical layer thicknesses, including fin/nanowire thickness changes as the current flows from source to channel and from channel to drain. We also explore different types of surface roughness due to plasma etch and lithography line edge roughness and its impact on transistor behavior. Quantum transport analysis suggests very non-intuitive engineering of surface roughness that can be transparent to the current flow for certain surface roughness patterns. The emerging role of atomic scale and quantum transport effects indicate a paradigm shift towards bandstructure driven transistor design. A key side effect of this is that the choice between different transistor architectures will come down to imperfections of different architectures and how these imperfections can be controlled and mitigated in high volume manufacturing environment. Atomic scale effects are inherently difficult to capture and quantify experimentally. Therefore, we use rigorous ab-initio physical approach to characterize such effects and extract guidelines for the future transistor design.
Speaker Biography
Victor Moroz received Ph.D. degree in Applied Physics from the University of Nizhny Novgorod in 1992 and joined a Stanford spin-off Technology Modeling Associates in 1995, which later became a part of Synopsys, connecting a design company to the manufacturing.
Currently Dr. Moroz is a Synopsys Fellow and Editor of Electron Device Letters, engaged in a variety of projects on analysis of advanced CMOS technology. Several facets of this activity are reflected in 100+ publications and 100+ granted and pending US patents.
************************************************************************************
September 11, 2018
“Mapping emerging memory devices to various applications: SCM, machine learning, in-memory computing, and other”
Speaker: Chris Petti, Fellow, Western Digital Corp.
Abstract
Over the years, there have been many technological candidates for a so-called “universal memory” – something that could replace NAND-FLASH, NOR-FLASH, SRAM, DRAM, etc. These technologies include many different types of resistive memory – oxide-based, conductive bridge, correlated electron, magnetic RAM, etc. Lately, it has become clear that none of these technologies is adequate for all of the usual Von-Neumann-based applications: storage (both “cold” or “hot”), main memory, cache, and other registers. Moreover, other, non-Von-Neumann based applications, including neural networks and in-memory computing, are being developed. The objective of this talk is to create a map of the different types of memory cell technologies to different applications and architectures, and to discuss the device and technology parameters that are most important for this classification.
Speaker Biography
Christopher Petti is an Engineering Fellow and Senior Director of Advanced Technology Development at Western Digital. He came to Western Digital as part of the acquisition of SanDisk in 2016. Dr. Petti has over 25 years of experience in a variety of semiconductor industries, including non-volatile memory, logic and SRAM technologies, flat-panel displays, and solar cells. In these fields, he has specialized in device physics, process integration, product architecture, and product engineering. Dr. Petti holds a B.S. in Physics from the Massachusetts Institute of Technology, and an M.S. and Ph.D. in Electrical Engineering from Stanford University. He is inventor or co-inventor on over 115 issued U.S. patents.
************************************************************************************
July 10, 2018
“Predicting Soft Errors and Hard Effects on ICs in Three Radiation Environments (On-the-Ground, In-Airplanes, and In-Space) Based on Accelerated, Accelerator Tests”
Speaker: Gary Swift, Swift Engineering and Radiation Services, LLC
Speaker Biography
Gary M. Swift received a B.S. in Engineering Physics from the University of Oklahoma in 1975 followed by graduate work in Nuclear Engineering at the University of Illinois at Urbana-Champaign. He tested electronic parts for radiation effects for almost two decades at NASA’s Jet Propulsion Laboratory in Pasadena -retiring as a principal engineer- and then for seven years at Xilinx, Inc. Currently, Gary is the Principal Engineer at the independent consulting firm Swift Engineering and Radiation Services, LLC which he founded. SwiftERS specializes in best-practice SEE testing of complex ICs such as FPGAs and microprocessors. He is an influential member of the radiation effects and testing community and has publications on a broad range of radiation effects testing including some on total dose and displacement damage, but most on single-event effects. For example, in 1992, he coined the now widely used term SEFI. Two papers he co-authored were given that year’s NSREC Outstanding Paper Award (1999 and 2015). In 2001, Gary co-founded the Xilinx Radiation Test Consortium, a voluntary group of national labs, universities and aerospace companies that collaborate on SEE testing; since then, he has served as XRTC test coordinator and weekly telecom moderator to the present day.
************************************************************************************
Special Event: IEEE EDS @ SJSU Technology Showcase
Saturday, May 19 , 2018
SJSU Student Union
211 S 9th St, San Jose, CA 95112
Free parking (code given by attendant) at SJSU North Parking Garage, 437 E San Fernando St. San Jose, CA 95112
Cost to attend: FREE
Agenda
8:30 ‐ 9:30: Free Continental Breakfast
9:00 ‐ 10:30: IEEE EDS Talk: “Emerging Interconnect Technologies for Nanoelectronics” by Prof. Krishna Saraswat, Department of Electrical Engineering, Stanford University
10:30 ‐ 12:30: SJSU Technology Showcase student project poster presentations
12:30 ‐ 2:30: Free Lunch/Panel Discussion
EDS Talk Abstract
Modern electronics has advanced at a tremendous pace over the course of the last half century primarily due to enhanced performance of MOS transistors due to dimension scaling, introduction of new materials and novel device structures. However, while this has enhanced the transistor performance, the opposite is true for the copper interconnects that link these transistors. Looking into the future the relentless scaling paradigm is threatened by the limits of copper/low-k interconnects, including excessive power dissipation, insufficient communication bandwidth, and signal latency for both off-chip and on- chip applications. Many of these obstacles stem from the physical limitations of copper/low-k electrical wires, namely the increase in copper resistivity, as wire dimensions and grain size become comparable to the bulk mean free path of electrons in copper and the dielectric capacitance. Thus, it is imperative to examine alternate interconnect schemes and explore possible advantages of novel potential candidates. This talk will address effects of scaling on the performance of Cu/low-k interconnects, alternate interconnect schemes: carbon nanotubes (CNT), graphene, optical interconnect, three-dimensional (3-D) integration and heterogeneous integration of these technologies on the silicon platform. Performance comparison of these technologies with Cu/low-k interconnects will be discussed. Prof. Saraswat is the is Rickey/Nielsen Chair Professor of Electrical Engineering at Stanford University.
SJSU Technology Showcase – student project topic areas
• Data Science (Data Mining/Machine Learning/Deep Learning)
• Smart City Apps and Technologies
• Blockchain
• Internet of Thing
• Embedded Systems/Robotics
• Enterprise App Development
• Cloud/Virtualization
• Cybersecurity
• Virtual and Augmented Reality
• ASIC/VLSI/Analog/Mixed-Signal Circuits
• Signal Processing
• Wireless Communications
• Smart Grid/Power Electronics/Control
• Electric Vehicles
************************************************************************************
April 16, 2018:
“The Smaller the Better: A Sub-Millimeter Wireless Neural Stimulator”
Speaker: Daniel Freeman, Principal MTS , Draper Lab, Cambridge, MA, USA
Abstract:
Wireless neural stimulators are being developed to address problems associated with traditional lead-based implants. However, designing wireless stimulators on the sub-millimeter scale (<1 mm3) is challenging. As device size shrinks, it becomes difficult to deliver sufficient wireless power to operate the device. To address this problem, we have developed a sub-millimeter, inductively powered neural stimulator consisting only of a coil to receive power, a capacitor to tune the resonant frequency of the receiver, and a diode to rectify the radio-frequency signal to produce neural excitation. By replacing any complex receiver circuitry with a simple rectifier, we have reduced the required voltage levels that are needed to operate the device from 0.5-1 V (e.g. for CMOS) to ∼0.25–0.5 V. This reduced voltage allows the use of smaller receive antennas for power, resulting in a device volume of 0.3–0.5 mm3. We have demonstrated the basic proof-of-concept with stimulation of both deep brain and peripheral nerve targets.
Biography:
Daniel Freeman is a Principal Member of the Technical Staff at Draper Laboratory in Cambridge, MA. He received his PhD in Biomedical Engineering from Boston University in 2008 where he investigated light adaptation mechanisms of the retina. This was followed by postdoctoral fellowships at MIT and Harvard Medical School in the area of retinal implants, where he developed methods to selectively excite individual types of neurons. At Draper, Dan has is been involved in a number of programs, including a sub-millimeter neural stimulator, a MEMS electrical field sensor, a mechanical antenna, and a microfluidic electroporation system. Dan currently runs a program on diamond vacuum transistors for rad-hard and low-noise electronics.
***************************************************************************************
December 5, 2017:
IEEE SCV-SF Electron Devices Society Seminar “Nano-Material Engineered Interconnect Technologies for Heterogeneous System Integration”
Prof. Mansun Chan, Hong Kong University of Science & Technology
An IEEE-EDS Distinguished Lecture
Nano-Material Engineered Interconnect Technologies for Heterogeneous System Integration
Mansun Chan
Dept. of ECE, Hong Kong University of Science & Technology,
Clear Water Bay, Kowloon, Hong Kong
E-mail: mchan@ust.hk
Abstract: The scaling of CMOS has encountered many hurdles in the sub-10nm technology nodes as we are approaching the end of the Moore’s Law. The performance limitations have shifted to the interconnect technology to reduce the metal wire resistance as well as the k-value of the interlayer dielectrics. The popular interconnect materials such as copper and tungsten have been found to be insufficient due to increasing resistivity with dimension scaling and electromigration concern under high current density. And using porous structures to form the interlayer dielectrics is subjected to the weakening of the mechanical strength of the dielectric film. New materials such as carbon nanotube (CNT) and graphene have been extensively studied to extend the scaling roadmap for interconnects. However, many barriers have to be overcome before these materials can enter mainstream manufacturing. In this presentation, I am going to present some of the recent progresses in using CNT as a contact plug as well as an agent to form very low k-value interlayer dielectrics.
Biography:
Prof. Mansun Chan received his BS in Electrical Engineering and Compute Science with highest honors from the University of California at San Diego and then completed his MS and PhD at the University of California at Berkeley. At Berkeley, was one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. Subsequently, he joined the Electrical and Electronic Engineering Department at Hong Kong University of Science and Technology. His research interests include emerging nano-device technologies, 2-D device for flexible electronics, Artificial Neural Network devices and applications, new-generation memory technology, BioNEMS, device modeling and ultra-low power circuit techniques. Between July 2001 and December 2002, he was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program. He is currently still consulting on the development of the next generation compact models.
Prof. Chan has been actively contributing to the professional community and hold many positions. He is a Board of Governor, Chair of the Education Committee, the Chair of the Region 10 subcommittee and a Distinguished lecturer of the IEEE Electron Device Society. He has also chaired many international conferences and acting as editors for a number of technical journals. In addition, he has received many awards including the UC Regents Fellowship, Golden Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship, R&D 100 award (for the BSIM3v3 project), Distinguished Teaching Award, the Shenzhen Science and Technology Innovation awards etc. He is a Fellow of HKIE, IET and IEEE.
*************************************************************************************
*************************************************************************************
*************************************************************************************
December 8:
IEEE SCV-SF Electron Devices Society Seminar “2D Electronics — Opportunities and Challenges”
Prof. Frank Schwierz, TU Ilmenau
An IEEE-EDS Distinguished Lecture
Location: Packard Building 101, Stanford University
Date: Friday December 8, 4:00 PM
Parking information:
https://transportation.stanford.edu/parking/about-parking-permits/view-parking-and-circulation-map
Visitors should park in the Via Ortega Garage, the Roble Field Garage, or the Roth Way Garage (in that order of preference) and parking is FREE after 4pm. (This is one of the reasons for having the seminar at that time.)
Abstract: During the past decade, 2D (two-dimensional) materials have attracted enormous attention from various scientific communities ranging from chemists and physicists to material scientists and device engineers. The rise of the 2D materials began in 2004 with the work on graphene done at Manchester University and Georgia Tech. Particularly the observed high carrier mobilities raised early expectations that graphene could be a perfect electronic material. It soon became clear, however, that due its zero bandgap graphene is not suitable for most electronic devices, in particular transistors. On the other hand, researchers have extended their work to 2D materials beyond graphene and the number of 2D materials under investigation is continuously rising. Many of them possess sizeable bandgaps and therefore are considered to be useful for transistors. Indeed, the progress in the field of 2D transistors has been rapid and experimental MOSFETs using semiconducting 2D channel materials have been reported by many groups. A recent achievement was the demonstration of a well-performing 1-nm gate MoS2 MOSFET in 2016. On the other hand, and in spite of the progress in the field, the debate on the real prospects of the 2D materials for future electronics is still controversial.
In the present lecture, the most important classes of 2D materials are introduced and the potential of 2D transistors is assessed as realistically as possible. To this end, two material properties – bandgap and mobility – are examined in detail and the mobility-bandgap tradeoff is discussed. The state of the art of 2D transistors is reviewed by summarizing relevant results of leading groups in the field, presenting examples of the lecturer’s own work on 2D electronics, and comparing the performance of 2D transistors to that of competing conventional transistors. Based on these considerations, a balanced view of both the pros and cons of 2D transistors is provided and their potential in both the More Moore (digital CMOS) and the More Than Moore domains of semiconductor electronics is discussed. It is shown that due to the rather conservative CMOS scaling scenario of the 2015 ITRS (compared to the more aggressive scenarios of the previous ITRS editions) it will be difficult for 2D materials to make inroads into mainstream CMOS. However, due to their specific properties (for example, 2D materials are bendable and stretchable) they may enable entirely new applications in the More Than Moore domain.
Bio: Frank Schwierz received the Dr.-Ing. and Dr. habil. degrees from Technische Universität (TU) Ilmenau, Germany, in 1986 and 2003, respectively. Presently he serves as Privatdozent at TU Ilmenau and is Head of the RF & Nano Device Research Group. His research interests include semiconductor device physics, novel device and material concepts for future transistor generations, and high-performance radio frequency transistors. At present he is particularly interested in two-dimensional electronic materials.
Dr. Schwierz is conducting research projects funded by the European Community, German government agencies, and the industry. Together with partners from academia and industry he was involved in the development of the fastest Si-based transistors worldwide in the late 1990s, of Europe’s smallest MOSFETs in the early 2000s, as well as of the fastestGaN HEMTs on Si and the fastest GaN tri-gate HEMTs worldwide in the 2010s. His recent work on two-dimensional materials made a major contribution to the current understanding of the merits and drawbacks of graphene transistors.
Dr. Schwierz has published more than 260 journal and conference papers including 40 invited papers. He is author of the books Modern Microwave Transistors – Theory, Design, and Performance (J. Wiley & Sons 2003) and Nanometer CMOS (Pan Stanford Publishing 2010) and editor of the book Two-Dimensional Electronics – Prospects and Challenges (MDPI 2016).
Dr. Schwierz is Senior Member of the IEEE. He serves as a Distinguished Lecturer of the IEEE Electron Devices Society and as an editor of the IEEE Transactions on Electron Devices. Moreover, he is one of the key contributors to the Emerging Research Devices Technology Working Groups of the 2013 and 2015 ITRS editions.
************************************************************************************
************************************************************************************
************************************************************************************
December 6:
IEEE SCV-SF Electron Devices Society co-sponsored workshop
“10th MOS-AK Compact Modeling Workshop in the Silicon Valley”
Time: December 6, 2017
Location: Cadence Office; Silicon Valley
Synopsis: The MOS-AK Association is organizing 10th successive compact modeling workshop in the timeframe of the IEDM and CMC Meetings on Dec.6, 2017 in Silicon Valley. The MOS-AK workshops are open HiTech forums to discuss the frontiers of electron device modeling with emphasis on simulation-aware models. MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all the important aspects of compact model development, implementation, deployment and standardization within the main theme – frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulations.
Topics: to be covered include the following:
• Advances in semiconductor technologies and processing
• Compact Modeling (CM) of the electron devices
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• FOSS TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT CMOS and SOI-based memory cells
• Organic, Bio/Med devices/technology modeling
• Microwave, RF device modeling, HV/Power device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and IC Designs
• Foundry/Fabless Interface Strategies
Online registration:
http://www.mos-ak.org/silicon_valley_2017
FOSS TCAD/EDA tools for advanced nano-device modeling
Wladek Grabinski
MOS-AK (EU)
Abstract:
Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.
Biography:
Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now an consultant responsible for modeling, characterization and parameter extraction of MOST devices for the IC design. He is currently consulting on the development of next-generation compact models for the nanoscaled technology very large scale integration (VLSI) circuit simulation. His current research interests are in high frequency characterization, compact modeling and its Verilog-A standardization as well as device numerical simulations of MOSFETs for analog/RF low power IC applications. He is an editor of the reference modeling book Transistor Level Modeling for Analog/RF IC Design and also authored or coauthored more than 50 papers. Wladek is the chair of the ESSDERC Track4: “Device and circuit compact modeling” as well as has served as a member of organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ. He is a Member At Large of Swiss IEEE ExCom and also supports the EPFL IEEE Student Branch acting as its Interim Branch Mentor. Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.
***************************************************************************************
***************************************************************************************
November:
IEEE SCV-SF Electron Devices Society Seminar “From Molecules to Pavlov’s Dog: Using Conjugated Polymers to Make Artificial Synapses”
Speaker: Dr. Prof. Alberto Salleo, Stanford University, USA
Date: Tuesday, November 14th, 2017
Contact: Vijay Narasimhan
Abstract:
The brain can perform massively parallel information processing while consuming only
~1- 100 fJ per synaptic event. Two-terminal memristors based on filament forming metal
oxides (FFMOs) or phase change memory (PCM) materials have recently been
demonstrated to function as non-volatile memory that can emulate neuronal and synaptic
functions. Despite recent progress in the fabrication of device arrays however, to date no
architecture has been shown to operate with the projected energy efficiency while
maintaining high accuracy. A major impediment still exists at the device level,
specifically, a resistive memory device has not yet been demonstrated with adequate
electrical characteristics to fully realize the efficiency and performance gains of a neural
architecture. I will describe a novel electrochemical neuromorphic device (ENODe) that
switches at record-low energy (<0.1 fJ projected, <10 pJ measured) and voltage (< 1mV,
measured), displays >500 distinct, non-volatile conductance states within a ~1 V
operating range, and achieves record classification accuracy when implemented in neural
network simulations. We recently showed that combined with a Si access device we are
able to achieve over 106 switching events with very little degradation. Our organic
neuromorphic device works by combining ionic (protonic) and electronic conduction and
is essentially similar to a concentration battery. The main advantage of this device is that
the barrier for state retention is decoupled from the barrier for changing states, allowing
for the extremely low switching voltages while maintaining non-volatility. Finally, plastic
ENODEs can be entirely fabricated on flexible substrates unlocking new opportunities
for integrating neuromorphic functionality in flexible and stretchable large-area
electronic systems, such as “smart skins”, that mimic the adaptive properties of biological
organs.
Biography:
Alberto Salleo is currently an Associate Professor of Materials Science at Stanford
University. Alberto Salleo graduated as a Fulbright Fellow with a PhD in Materials
Science from UC Berkeley in 2001. From 2001 to 2005 Salleo was first post-doctoral
research fellow and successively member of research staff at Xerox Palo Alto Research
Center. In 2005 Salleo joined the Materials Science and Engineering Department at
Stanford as an Assistant Professor and was promoted to Associate Professor in 2013.
Salleo is a Principal Editor of MRS Communications since 2011. He has published over
170 peer-reviewed articles, co-authored 8 book chapters and co-edited a book on flexible
electronics. In 2015 and 2016 he was a Thomson Reuters Highly Cited Researcher in
Materials Science (top 1% citations in the field).
While at Stanford, Salleo won the NSF Career Award, the 3M Untenured Faculty Award,
the SPIE Early Career Award and the Tau Beta Pi Excellence in Undergraduate Teaching
Award and the Gores Award for Excellence in Teaching, Stanford’s highest teaching
honor.
****************************************************************************************
October:
IEEE SCV-SF Electron Devices Society Seminar “Reliability challenges for the qualification of Leading Edge CMOS Technologies”
Speaker: Dr. Fernando Guarín, IEEE Fellow, Distinguished Member of technical Staff, GlobalFoundries East Fishkill, NY. USA
Date: Tuesday, October 10th, 2017
Contact: Victor Cao
Abstract:
This presentation will address some of the key reliability challenges during the qualification of leading edge CMOS technologies. Some of the issues are driven by self heating in SOI and some by the latest trends in semiconductor fabrication as we continue to scale and deal with the new reliability challenges introduced by the use of High K Metal Gate (HKMG) and FinFet devices. We will discuss the reliability impact and the qualification activities driven by the introduction of SOI and new materials. The path to maintaining the advanced CMOS scaling cadence and new reliability limiting factors will be examined from the reliability perspective. A closer look will be given to Hot Carriers, Bias Temperature Instabilities and Gate Dielectric Integrity. The characterization, models and qualification methodologies will be put in the required perspective for the successful qualification and transfer of leading edge technologies to a manufacturing environment.
Biography:
Dr. Fernando Guarín is a Distinguished Member of Technical Staff at Global Foundries in East Fishkill NY. He retired from IBM’s Semiconductor Research Development Center after 27 years as Senior Member of Technical Staff. He earned his BSEE from the “Pontificia Universidad Javeriana”, in Bogotá, Colombia, the M.S.E.E. degree from the University of Arizona, and the Ph.D. in Electrical Engineering from Columbia University, NY He has been actively working in microelectronic reliability for over 35 years. From 1980 until 1988 he worked in the Military and Aerospace Operations division of National Semiconductor Corporation. In 1988 he joined IBM’s microelectronics division where he worked in the reliability physics and modeling of Advanced Bipolar, CMOS and Silicon Germanium BiCMOS technologies. Dr. Guarín is an IEEE Fellow, Distinguished Lecturer for the IEEE Electron Device Society, where he has served in many capacities including; member of the IEEE’s EDS Board of governors, chair of the EDS Education Committee, Secretary for EDS. He is the EDS President-Elect 2016-2017.
Aug 8th, 2017 | Recent Progress in Memory Technology ReliabilitySpeaker: Dr. Bob Gleixner, Micron Technology Inc.Link to slides |
July 11th, 2017 | System Level ESD: A New FocusSpeaker: Dr. Charvaka Duvvury, ESD ConsultingLink to slides |
June 13th, 2017 | Device and Process VariabilitySpeaker: Dr. Tomasz Brozek, Technical Fellow and Engagement Director at PDF Solutions, San Jose, CALink to slides |
May 9th, 2017 | New Visions for IC Yield Detractor DetectionSpeaker: Bill Nehrer, VP and Account General Manager, PDF Solutions, San Jose, CA |
March 14th, 2017 | Progress Toward Wafer-Scale Thermionic Energy ConvertersSpeaker: Prof. Roger Howe, Dept. of Electrical Engineering, Stanford Nano Fabrication Facility, Stanford University |
2016 Past Events
Dec 1st, 2016 | On-Chip ESD Protection Design: Yesterday, Today, Tomorrow and FutureSpeaker: Prof. Albert Wang, University of California, Riverside |
Nov 11th, 2016 | IEEE SCV-SF EDS Annual Symposium Device Circuit Interaction in Advanced Technology Nodes |
Oct 11th, 2016 | Time-Zero and Time-Dependent Variability in Advanced CMOSSpeaker: Dr. Jeffrey T. Watt, Intel Fellow, Intel Corp. Lecture slides |
Sept 30th, 2016 | Mini-colloquium Emerging Devices, Materials and Technologies Speaker(s): Leading scientists and engineers, including EDS Distinguished Lecturers |
Aug 9th, 2016 | Circuit Device Interactions and co-optimizations, from system and chip design to process integration – The secret sauce for complex SOC chips and SIPs in advanced technology nodesSpeaker: Dr. John Hu, Director of Advanced Technology, Nvidia Corp., Santa Clara, CA |
July 12th, 2016 | Electronics and Energy Applications of 1D and 2D NanomaterialsSpeaker: Dr. Eric Pop, Associate Professor of Electrical Engineering , Stanford University, Stanford CALecture slides |
May 10th, 2016 | Designing with FinFETsSpeaker: Dr. Witold (Witek) P. Maszara, GLOBALFOUNDRIES, Santa Clara, CA |
June 14th, 2016 | High Frequency Characterization of TransistorsSpeaker: Dr. Jayasimha Prasad, Device/Process Integration Engineer, Foveon Inc, San Jose CALecture slides |
Apr. 12th, 2016 | Learnings and insights from 52 years of Silicon Valley semiconductor experienceSpeaker: Ray Zinn, Founder and CEO of Micrel, San Jose, CAVideo recording of presentation |
Mar. 8, 2016 | Technology CAD from Electronics to BioelectronicsSpeaker: Dr. Yang Liu, Professor at the College of Information Science and Electronic Engineering, Zhejiang University, China |
Feb. 9, 2016 | Everything You Wish to Know about Memristors But Are Afraid to Ask Speaker: Dr. Leon Chua, Professor of EECS, University of California, BerkeleyLecture links |
2015 Past Events
May. 19, 2015 | Nanoscale Vacuum ElectronicsSpeaker: Dr. Meyya Meyyappan, Chief Scientist for Exploration Technology at NASA Ames Research Center in Moffett Field, CA |
Feb. 10, 2015 | A photovoltaic diode array as a retinal prosthesis for patients with degenerative retinal diseasesSpeaker: Dr.Theodore I. (Ted) Kamins, Stanford University IEEE SCV Electron Devices SocietyIEEE Photonics Society co-sponsoredAbstract/bio Slides |
2014 Past Events
August 12, 2014 | Graphene and Beyond-Graphene 2D Crystals for Next-Generation Green ElectronicsSpeaker: Dr. Kaustav Banerjee, University of California, Santa BarbaraIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio Directions |
July 29, 2014 | Mesoscopic Devices and Their Impact on Product Yield: The Next Technological Challenge Speaker: Dr. Renuka P. Jindal, Fellow, IEEE, University of Louisiana at Lafayette, LA, USA IEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio Directions |
June 10, 2014 | Parallel Revolutions: How Breakthroughs in Electronics and Biology are Converging at the Molecular ScaleSpeaker: Dr. Jim Hollenhorst, Agilent TechnologiesIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio Slides (with video link) |
April 15, 2014 | System Level On-Chip ESD ProtectionSpeaker: Dr. Vladislav Vashchenko, Maxim Integrated CorpIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio Slides |
March 11, 2014 | The Roadmap to Success: 2013 ITRS UpdateSpeaker: Dr. Paolo Gargini, Chairman of ITRS and IEEE/IEC/Intel FellowIEEE SCV Electron Devices SocietyCo-sponsored by SF Bay Area Nanotechnology Council Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio Slides |
March 5, 2014 | Bionic Skins with Ulraflexible Organic DevicesSpeaker: Takao Someya, School of Engineering, The University of Tokyo, 3-7-1 Hongo, Bunkyo-ku, Tokyo, JapanStanford University and IEEE SCV Electron Devices Society Location: the Allen Building room 101X, Stanford UniversityTime: 4:15pm Abstract/bio |
Feb 18, 2014 | Product Level Reliability Challenges Originating from TDDB, BTI and VariabilitySpeaker: Dr. Tanya Nigam, GlobalFoundriesIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio Directions |
November 2013 | |||||||||||||||||||||||||||||
Nov 19, 2013 | Eastern Europe’s Semiconductor Technology – Recollections and Projections Speaker: Dr. C. BuluceaIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio Slides |
||||||||||||||||||||||||||||
October 2013 | |||||||||||||||||||||||||||||
Oct 8, 2013 | How far can we push Si CMOS and what are the alternatives for future ULSI Speaker: Prof. K. Saraswat, Stanford UniversityIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio Slides |
||||||||||||||||||||||||||||
September 2013 | |||||||||||||||||||||||||||||
Sept 24, 2013 | Low Power Circuit Design Techniques for Nano-Scale Era Speaker: Dr. R. V. Joshi, IBMIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio |
||||||||||||||||||||||||||||
September 2013 | |||||||||||||||||||||||||||||
Sept 6, 2013 | Annual SymposiumPower Electronics: Beyond the Silicon LimitAbstract: Power electronics is re-emerging as an important and innovative area. This is due to the increasing importance of electricity in our lives, and the need to use it more efficiently. … (click to read more) Speakers:Deva Pattanayak (Senior Director at Vishay Siliconix)Alex Lidow (CEO of EPC)Dave Anderson (Chief Technologist and General Manager of Texas Instruments Kilby Labs Silicon Valley)Johan Strydom (Head of Applications Engineering at EPC)Don Disney (Sr. Director of Technology and Product Development atAvogy)Abstracts/bio |
||||||||||||||||||||||||||||
July 2013 | |||||||||||||||||||||||||||||
Jul 9, 2013 | Memristive Devices for Computing Speaker: Dr. J. Joshua Yang, Hewlett Packard LaboratoriesIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio |
||||||||||||||||||||||||||||
June 2013 | |||||||||||||||||||||||||||||
Jun 11, 2013 | A Complete NBTI DC / AC Model for SiON and HKMG p-MOSFETs Speaker: Prof. Souvik Mahapatra, Indian Institute of Technology Bombay, MumbaiIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio |
||||||||||||||||||||||||||||
April 2013 | |||||||||||||||||||||||||||||
Apr 9, 2013 | High-Efficiency, Flexible, Thin-Film, III-V Solar Cells Speaker: Dr. Brendan Kayes, Alta DevicesIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio |
||||||||||||||||||||||||||||
March 2013 | |||||||||||||||||||||||||||||
Mar 12, 2013 | Electronics Applications of Carbon Nanotube and Graphene Speaker: Prof. H.-S. Philip Wong, Stanford UniversityIEEE SCV Electron Devices Society, co-sponsored by IEEE SFBA Nanotechnology Council Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Time: 6 PM – Pizza, 6:15 PM – talk Abstract/bio |
||||||||||||||||||||||||||||
February 2013 | |||||||||||||||||||||||||||||
Feb 12, 2013 | Towards Storage Class Memory: 3-D crosspoint access devices using Mixed-Ionic-Electronic-Conduction (MIEC) Speaker: Dr. Geoffrey W. Burr, IBM Almaden Research CenterIEEE SCV Electron Devices Society, co-sponsored by IEEE SFBA Nanotechnology Council Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bio Slides |
||||||||||||||||||||||||||||
November 2012 | |||||||||||||||||||||||||||||
November 13, 2012 | Analog Technologies: Status & Opportunities Speaker: Dr. Albert Bergemont, Vice President of Technology, Research & Development, Maxim Integrated Products.IEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bio |
||||||||||||||||||||||||||||
October 2012 | |||||||||||||||||||||||||||||
October 9, 2012 | Device Considerations for Low Power VLSI Circuits Speaker: Dr. Robert Rogenmoser, Senior Vice President, Product Development and Engineering, SuVolta, Inc.IEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bioPresentation Slides |
||||||||||||||||||||||||||||
August 2012 | |||||||||||||||||||||||||||||
August 14, 2012 | Nanoscale CMOS Contacts: Science and Technology Speaker: Dr. Khaled Ahmed, Applied MaterialsIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bio |
||||||||||||||||||||||||||||
June 2012 | |||||||||||||||||||||||||||||
June 18, 2012 | A Unified Compact Model for Generic Heterostructure HEMTs Speaker: Dr. Xing Zhou, School of Electrical & Electronic EngineeringNanyang Technological University, SingaporeIEEE SCV Electron Devices Society Distinguished Lecture Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bioPresentation Slides |
||||||||||||||||||||||||||||
May 2012 | |||||||||||||||||||||||||||||
May 8, 2012 | Next Generation Photovoltaics Speaker: Prof. Sue A. Carter, Physics Department, University of California, Santa CruzIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052. Abstract/bio |
||||||||||||||||||||||||||||
April 2012 | |||||||||||||||||||||||||||||
April. 10, 2012 | 2D Carbon/Semiconductor-Enabled Electronics Speaker: Prof. Bin Yu, College of Nanoscale Science & Engineering, State University of New York – AlbanyIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052. Abstract/bioPresentation Slides |
||||||||||||||||||||||||||||
March 2012 | |||||||||||||||||||||||||||||
Mar. 20, 2012 | FinFET/Trigate FET and Its SPICE Model Speaker: Professor Chenming Hu, EECS, UC Berkeley, CA, USAIEEE SCV Electron Devices Society Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bioPresentation Slides |
||||||||||||||||||||||||||||
February 2012 | |||||||||||||||||||||||||||||
Feb. 15, 2012 | 2011 International Technology Roadmap for Semiconductors (ITRS) Update – Overview and Highlights Speaker: Alan K. Allan, Intel Corporation, Chandler, AZ, USAIEEE SCV Electron Devices Society, co-sponsored by IEEE SFBA Nanotechnology Council Location: Texas Instruments Building E Conference Center2900 Semiconductor Dr. Santa Clara, CA 95052.Abstract/bioPresentation Slides |
||||||||||||||||||||||||||||
November 2011 Half-Day Symposium | |||||||||||||||||||||||||||||
Nov. 4, 2011 | Current Status and Future Directions of Non‐Volatile Memory Technology Invited Speakers:Dr. Gurtej Sandhu, MicronDr. Al Fazio, IntelDr. Chuck Dennison, OvonyxProfessor Michael Kozicki, Arizona State UniversityDr. Joshua Yang, HP Laboratories.IEEE Santa Clara Valley Electron Devices Society Location: Texas Instruments, Building E1, Conference Center,2900 Semiconductor Drive, Santa Clara, CA 95051.AnnouncementSpeakers’ BiographiesTalk abstractAgenda |
||||||||||||||||||||||||||||
October 2011 | |||||||||||||||||||||||||||||
Oct. 13, 2011 | The Variability Issues in Advanced CMOS: Random Dopant Fluctuation and Random Trap Fluctuation Speaker: Professor Steve S. Chung, Department of Electronics Engineering, National Chiao Tung University, Taiwan. IEEE Fellow, Distinguished LecturerIEEE SCV Electron Devices Society Distinguished Lecture Program Location: Kenna 214, Santa Clara University (direction linked below).Abstract/bioPresentation Slides |
||||||||||||||||||||||||||||
October 2011 | |||||||||||||||||||||||||||||
Oct. 11, 2011 | Carbon Electronics – From Material Synthesis to Circuit Demonstration Speaker: Professor H.-S. Philip Wong, Center for Integrated Systems and Department of Electrical Engineering, Stanford UniversityIEEE SCV Electron Devices Society and IEEE SFBA Nanotechnology Council Location: Texas Instruments Abstract/bioPresentation Slides |
||||||||||||||||||||||||||||
September 2011 | |||||||||||||||||||||||||||||
Sept. 13, 2011 | Metal interconnects for large-area power devices – physics, challenges, and solutions Speaker: Dr. Maxim Ershov, CTO, Silicon Frontline TechnologiesIEEE SCV Electron Devices Society Location: National SemiconductorAbstract/bio |
||||||||||||||||||||||||||||
August 2011 | |||||||||||||||||||||||||||||
August 09, 2011 | Graphene – Still Heading for Prime Time Speaker: Prof. Zhiping Yu, Institute of Microelectronics, Tsinghua University, Beijing, ChinaIEEE SCV Electron Devices Society Location: National Semiconductor.Abstract/bio Presentation Slides |
||||||||||||||||||||||||||||
June 2011 | |||||||||||||||||||||||||||||
June 14, 2011 | Simulation of Statistical Variability and Reliability: From TCAD to Statistical Circuit Simulation Speaker: Prof. Asen Asenov, FIEEE, FRSE; Leader of the Device Modeling Group, University of Glasgow; CEO of Gold Standard Simulations LtdIEEE SCV Electron Devices Society and IEEE SFBA Nanotechnology Council Location: National Semiconductor Abstract/bioPresentation Slides |
||||||||||||||||||||||||||||
May 2011 | |||||||||||||||||||||||||||||
May 10, 2011 | Characterization and Modeling of NBTI Stress, Recovery, Material Dependence and AC Degradation Using R-D Framework Speaker: Professor Souvik Mahapatra, Department of Electrical Engineering, IIT Bombay, IndiaIEEE SCV Electron Devices Society Location: National Semiconductor Abstract/bio Location map and directions |
||||||||||||||||||||||||||||
April 2011 | |||||||||||||||||||||||||||||
April 14, 2011 | Future ESD Challenges for IC Components and Systems Speaker: Dr. Charvaka Duvvury, Texas Instruments (Dallas, USA), EDS Distinguished Lecturer IEEE SCV Electron Devices Society Distinguished Lecture, cohosted by Stanford IEEE and TCAD group Location: Stanford University, Paul G. Allen Building Annex, Auditorium 101 Abstract/bio Presentation Slides |
||||||||||||||||||||||||||||
April 2011 | |||||||||||||||||||||||||||||
April 5, 2011 | The History of Flash Memory Technology and What Lies Ahead Speaker: Ishai Naveh, Adesto Technologies IEEE SCV Electron Devices Society Location: National SemiconductorAbstract/bio |
||||||||||||||||||||||||||||
March 2011 | |||||||||||||||||||||||||||||
Mar. 1, 2011 | Lithography Options for 22nm and Beyond Speaker: Dr. Geert Vandenberghe, imec IEEE SCV Electron Devices Society Location: National Semiconductor Abstract/bio |
||||||||||||||||||||||||||||
Feb 2011 | |||||||||||||||||||||||||||||
Feb. 8, 2011 | Photovoltaic Module Reliability and Failure Analysis: Enduring a storm Dr. Glenn Alers, University of California at Santa Cruz IEEE SCV Electron Devices Society, co-sponsored by IEEE SCV Reliability Society Location: National Semiconductor Abstract/bioSpeaker slides |
||||||||||||||||||||||||||||
Jan 2011 | |||||||||||||||||||||||||||||
Jan. 11, 2011 | Mechanical Computing Redux: Relays for Integrated Circuit Applications Prof. Tsu-Jae King Liu, Dept. of EECS, UC Berkeley IEEE SCV Electron Devices Society Location: National Semiconductor Abstract/bio |
||||||||||||||||||||||||||||
Dec 2010 | |||||||||||||||||||||||||||||
Dec. 2, 2010 | Millibits to Terrabits per second and Beyond – Over 60 Years of Innovation Dr. Renuka Jindal, Distinguished Lecture by IEEE Electron Devices Society President IEEE SCV Electron Devices Society Location: Santa Clara University Abstract/bio |
||||||||||||||||||||||||||||
Nov 2010 | |||||||||||||||||||||||||||||
Nov 16, 2010 | Resistive RAM: Technology and Market Opportunities Deepak Sekar, NuPGA Corporation IEEE SCV Electron Devices Society Location: National Semiconductor Abstract/bio Speaker slides |
||||||||||||||||||||||||||||
Nov 16, 2010 | Nanoelectronics: Innovation and Implementation Half-day symposium by the Nanotechnology Council, co sponsored by EDS Location: National Semiconductor For available presentations |
||||||||||||||||||||||||||||
Oct 2010 | |||||||||||||||||||||||||||||
Oct 12, 2010 | Is it the End of the Road for Silicon in Power Management? Dr. Alex Lidow, CEO Efficient Power Conversion Corporation IEEE SCV EDS and PELS societies Location: National Semiconductor, Abstract/bio Speaker slides |
||||||||||||||||||||||||||||
Oct 18, 2010 | Intellectual Property (IP) Primer for Entrepreneurs and Early-Stage Companies Jordan M. Becker, Partner, Perkins Coie IEEE SCV CAS and EDS societies Location:QualComm Santa Clara, Building B Abstract/bio Speaker slides |
||||||||||||||||||||||||||||
Oct 28, 2010 | Second Annual IEEE-SCV Soft Error Rate (SER) Workshop Chiate Lin, Intersil; Prof. Bharat Bhuva, Vanderbilt U.; Rick Wong, Cisco Systems;Dr Andy Mackie, Indium Corp.; Charles Slayman, Ops a la Carte; Dr. Brett Clark, Honeywell; Dr. Nelson Tam, Marvell IEEE SCV CPMT/EDS/Rel societies Location: Cisco or webinar CPMT web page – slides etc. |
||||||||||||||||||||||||||||
Sept 2010 | |||||||||||||||||||||||||||||
Sept 14, 2010 | LDMOS – Technology and Applications Shekar Mallikarjunaswamy, Alpha Omega Semiconductor IEEE SCV EDS seminar Location: National Semiconductor 2900 Semiconductor Drive , Santa Clara , CA 95052 Abstract/bio Speaker slides |
||||||||||||||||||||||||||||
Sept 28, 2010 | The Makers of the Microchip: Creating the Planar Integrated Circuit, Establishing Silicon Valley David Brock, Research Fellow, Chemical Heritage Foundation Christophe Lecuyer, Principal Economic Analyst, UC Co-sponsored with IEEE SSC+CS Location: National Semiconductor Abstract/Bio/Registration |
||||||||||||||||||||||||||||
Aug 2010 | |||||||||||||||||||||||||||||
Aug 10, 2010 | 3-D ICs: Motivation, Performance Analysis, Technology and Applications Dr. Krishna Saraswat, IEEE Fellow, Dept. of Electrical Engineering, Stanford University IEEE SCV EDS and CPMT societies Location: National Semiconductor, Building E-1, Conference Center Abstract/bio Speaker slides |
||||||||||||||||||||||||||||
July 2010 | |||||||||||||||||||||||||||||
July 13, 2010 | The Foundation of Today’s Digital World: The Triumph of the MOS Transistor Ross Bassett, Lewis M. Terman, Les Vadasz, David A. Hodges IEEE and CHM Location: Computer History Museum. Registration and further info |
||||||||||||||||||||||||||||
Jun 2010 | |||||||||||||||||||||||||||||
Jun 7, 2010 | New Driving Force for Electromigration in ULSI Interconnections and its implication to IC layout Dr. Cher Ming Tan – School of EEE, Nanyang Technological University, Singapore IEEE SCV EDS seminar Location: National Semiconductor Abstract/bio Speaker slides |
||||||||||||||||||||||||||||
Jun 18, 2010 | Nanoscale Manipulation of Conductive Filaments in Solid-Electrolyte-Based-ReRAM Prof. Ming Liu, Institute of Microelectronics, Chinese Academy of Science (IMECAS), China. IEEE SCV EDS seminar Location: Santa Clara University 500 El Camino Real, Santa Clara, CA 95053 Abstract/bio Speaker slides |
||||||||||||||||||||||||||||
May 2010 | |||||||||||||||||||||||||||||
May 20, 2010 | Trends in Solar Cell Technology Dr. Betty Prince (New Energy Strategies International) IEEE SCV Solid-State Circuits (SSC) and Electron Devices Societies (EDS) Location: National Semiconductor IEEE SSC event page |
||||||||||||||||||||||||||||
May 11, 2010 | Thoughts on Directions for Silicon Technology Development as We Approach the End of CMOS Scaling Tak H. Ning, IBM and IEEE Fellow, and co-author of the Taur & Ning textbook IEEE SCV EDS seminar Location: National Semiconductor 2900 Semiconductor Drive , Santa Clara , CA 95052 Abstract/bio Speaker Slides |
||||||||||||||||||||||||||||
Apr 2010 | |||||||||||||||||||||||||||||
Apr 13, 2010 | The Semiconductor Industry’s Nanoelectronics Research Initiative (NRI): Motivation and Overview Jeff Welser, IBM/Executive Director of NRI IEEE SCV EDS seminar Location: National Semiconductor, Building E-1, Conference Center Abstract/bio Speaker Slides |
||||||||||||||||||||||||||||
Mar 2010 | |||||||||||||||||||||||||||||
Mar 16, 2010 | 2009 International Technology Roadmap for Semiconductors (ITRS) Update – Overview and Highlights Alan K. Allan – SEMATECH IEEE SCV EDS seminar Location: National Semiconductor, Building E-1, Conference Center Abstract/bio Speaker slidesPhoto below with one of the first fifty 450 mm wafers ever (wafer made by Nippon Mining & Metals). |
||||||||||||||||||||||||||||
Feb 2010 | |||||||||||||||||||||||||||||
Feb 16, 2010 | High Frequency Characterization of Transistors J. Prasad, SuVolta Inc, Los Gatos, CA IEEE SCV EDS seminar Location: National Semiconductor, Building E-1, Conference Center Abstract/bio Click here for slides |
||||||||||||||||||||||||||||
Jan 2010 | |||||||||||||||||||||||||||||
Jan 29, 2010 | 3D Interconnect – Shaping Future Technology Full-day symposium with many exciting talks Location: Hyatt Regency, 5101 Great America Pkwy, Santa Clara , CA 95054 Symposium: 9 AM – 5 PM Reception/Poster session: 5 – 6:30 PM Cost: Free. Refreshments and Lunch provided Click here for flyer Click here for Agenda Click here for Abstracts/bio.List of speakers: (slides available as posted)
|
For talks before Jan. 2010, please click here