Santa Clara Valley-San Francisco Chapter of Electron Devices Society (Silicon Valley, California)



Welcome to Electron Devices Society–Santa Clara Valley/San Francisco Chapter

IEEE-EDS September Seminar (Webex only)

Title: Design and Modelling Challenges for Very Large-Scale Integrated Quantum Processors in Foundry CMOS Technologies

Speaker: Sorin P. Voinigescu

Friday, November 18th, 2022 at noon – 1PM PDT

Register Here

Webex link will be distributed to the registrant via email.
Organizer contact: Hiu Yung Wong (hiuyung.wong at


This presentation will discuss the main challenges in the physical implementation, design, hierarchical modelling and simulation of the scalable qubit array and of the cryogenic control and readout electronics for future Quantum Processors with millions of qubits manufactured in commercial FDSOI and FinFET foundry technologies. Impact of process manufacturing rules restrictions and process variation on qubit design and modelling, circuit heat dissipation and layout miniaturization to fit the qubit array pitch, qubit-to-qubit crosstalk, and the need for atomistic, classical, and behavioural qubit simulation and modelling will be covered in detail.

Speaker Bio:

Sorin P. Voinigescu is a Professor in the Electrical and Computer Engineering Department at the University of Toronto where he holds the Stanley Ho Chair in Microelectronics and is the Director of the VLSI Research Group. He is an IEEE Fellow and an expert on millimeter-wave and 100+Gb/s integrated circuits and atomic-scale semiconductor device technologies. He obtained his PhD degree in Electrical and Computer Engineering from the University of Toronto in 1994 and his M.Sc. Degree in Electronics and Telecommunications from the Politechnical Institute of Bucharest in 1984.


More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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