May 10th, 2016 seminar on Designing with FinFETs

IEEE SCV Electron Devices Society May 10th, 2016 Seminar by Dr. Witold (Witek) P. Maszara, GLOBALFOUNDRIES, Santa Clara, CA

“Designing with FinFETs” 


IEEE SCV Electron Devices Society Seminar “Designing with FinFETs”

Speaker: Dr. Witold (Witek) P. Maszara, Distinguished Member of Technical Staff, GLOBALFOUNDRIES, Santa Clara, CA

Tuesday, May 10th, 2016

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments
6:15 – 7:00 PM: Seminar 

Cost: Free
Location: Texas Instruments Building E Conference Center

2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building
location map and directions
Contact: Victor Cao

Web link:


FinFET, a fully depleted, multigate transistor entered the market with high performance microprocessor product at 22nm node in 2012 and became standard device for scaled technologies. FinFETs offer superior performance over incumbent planar devices due to their significantly improved electrostatics. FinFET technology faced two key barriers to their implementation in products: demanding process integration and its significant impact on layout and circuit design methodology. In this presentation we focus on key features and challenges in designing with FinFETs. Fin formation, metrology, device parasitics, performance as well as design challenges for logic and SRAM circuits will be discussed.

Witold (Witek) P. Maszara has received MS degree in Electronics from Technical University of Wroclaw, Poland, and PhD degree from University of Kentucky in EE. Co-author of 100+ papers, author of over 50 invited talks and seminars, and over 60 patents in the field of microelectronics. Served as Technical Program Chair and General Chair of IEEE International SOI Conference, Chair of IEEE IEDM’s Subcommittee for Integrated Circuits and Manufacturing . Served on technical committees for SOI Conference, IEDM and VLSI Symposium on Technology. Member of technical advisory boards for Semiconductor Research Corporation, Sematech, National Science Foundation, INMP, SystemX and IMEC (Belgium) for broad range of semiconductor technology programs. Current areas of interest: CMOS logic technology, dense embedded memory. He is presently employed at GLOBALFOUNDRIES as Distinguished Member of Technical Staff. He is IEEE Fellow.

More information at the IEEE Santa Clara Valley EDS Chapter Home Page

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