May 9th, 2017 New Visions for IC Yield Detractor Detection Bill Nehrer, VP and Account General Manager, PDF Solutions

IEEE SCV-SF Electron Devices Society May 9th, 2017 Seminar by Bill Nehrer, PDF Solutions, San Jose, CA

New Visions for IC Yield Detractor Detection 

IEEE SCV-SF Electron Devices Society Seminar “New Visions for IC Yield Detractor Detection”

Speaker: Bill Nehrer, VP and Account General Manager, PDF Solutions, San Jose, CA


Time: 6:00 PM – 6:15 PM: Networking with food and refreshments

6:15 – 7:00 PM: Seminar 

Cost: Free

Location: Texas Instruments Building E Conference Center
2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building
location map and directions

Contact: Sachin Sonkusale

Web link:


The observability of conventional electrical test site and imaging techniques needs to be extended and coupled with all of the actual product layout attributes in order to reflect the relevant yield detractors of the current technologies in production and development. This talk presents new electrical test site strategies that have been recently developed and deployed developed for parametric yield detection and systematic hard defect detection by layout attribute. Such test structures are derived from the actual product and in some key cases also embedded in the product utilizing available space between the active circuitry and detected in-line with non-contact techniques.


Bill Nehrer has developed a variety of technologies, primarily analog focused, over his 30+ years in the semiconductor industry. They span analog CMOS to High Speed BiCMOS and Bipolar, enabling world class products in phased array radar,  early audio/video single chip solutions,  high speed modem,  hard disk drive,  Medium voltage power management, and high resolution ADCs. His focus was High Reliability along with yield optimization mass production. In recognition,  he was elected technical Fellow at Silicon Systems, a Texas Instruments company. As the manager of Texas Instruments’ High Precision Analog and High Speed Bipolar roadmap, he directed multiple projects at various worldwide TI locations.  Joining PDF Solutions in 2004,  he has since managed yield ramp and technology development consulting projects at leading logic fabs in 90, 65, 45, 32, 28, 20, 14, & 10nm technology,  currently holding the title of VP and Account General Manager responsible for establishment of new projects and the technical operations afterwards.   Bill holds an MSEE degree in Solid State Electrophyics from the University of Southern California.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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