February 7th, 2017 Buried-Halo MOSFETs for Ultra-Low Power Application at Nano Nodes

IEEE SCV-SF Electron Devices Society February 7th, 2017 Seminar by Dr. Samar K. Saha, Prospicient Devices

“Buried-Halo MOSFETs for Ultra-Low Power Application at Nano Nodes” 

IEEE SCV-SF Electron Devices Society Seminar “Buried-Halo MOSFETs for Ultra-Low Power Application at Nano Nodes”

Speaker: Dr. Samar K. Saha, Prospicient Devices, Milpitas, CA

Tuesday, Feb 7th, 2017

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments

6:15 – 7:00 PM: Seminar 

Cost: Free

Location: Texas Instruments Building E Conference Center
2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building
location map and directions

Contact: Victor Cao

Web link: http://site.ieee.org/scv-eds/


In this talk the device/process architecture and modeling of buried-halo MOSFET (BH-MOSFET) devices for low power application are discussed. The continuous scaling of planar MOSFETs towards 5-nm regime has become more challenging due to fundamental device-physics constraints including short-channel effect (SCE) and process-variability. The SCE degrades the performance of scaled devices with higher sub-threshold swing and leakage current and poses a sever challenge to control device performance by gate bias. On the other hand, the process variability severely impacts the delay and power variability in VLSI devices, circuits, and chips. The impact of the increasing amount of within-die process variability on the yield of VLSI circuits, such as SRAM, has imposed an enormous challenge to design advanced VLSI chips using bulk-CMOS technology. In order to mitigate the risk of process variability, new statistical design methodologies have evolved. Though, these statistical modeling techniques allow designers best possible solution to optimize the impact of variability, however, process variability constraint limits the circuit performance and yield. However, to mitigate the risk of process variability, variability-tolerant device architecture is required. In this talk, the architecture and modeling of BH-MOSFET devices for continuous scaling of planar MOSFETs in the nano nodes will be discussed.


Dr. Samar K. Saha is currently, President of IEEE Electron Devices Society (EDS). He is an Adjunct faculty in the Electrical Engineering department at Santa Clara University and a technical advisor at Prospicient Devices. Since 1984, he has worked at various positions for National Semiconductor, LSI Logic, Texas Instruments, Philips Semiconductors, Silicon Storage Technology, Synopsys, DSM Solutions, Silterra USA, and SuVolta. He has, also, worked as a faculty member in the Electrical Engineering departments at Southern Illinois University at Carbondale, Illinois; Auburn University, Alabama; the University of Nevada at Las Vegas, Nevada; and the University of Colorado at Colorado Springs; Colorado. He has authored more than 100 research papers; one book entitled, Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond, CRC Press, Florida (2015); one book chapter on Technology Computer-Aided Design (TCAD), entitled, Introduction to Technology Computer-Aided Design, in Technology Computer Aided Design: Simulation for VLSI MOSFET, C.K. Sarkar (ed.): CRC Press, Florida (2013), and holds 10 US patents. His research interests include nanoscale device and process architecture, TCAD, compact modeling, devices for renewable energy, and TCAD and R&D management.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

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