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2017 Events

“Silicon is the New Steel: Building the Internet of Everything — The World’s First Terascale Network” by SSCS Distinguished Lecturer, Tom Lee, from Stanford University.

Date: March 16th, 2017

IEEE SCV CAS proudly co-sponsors an IEEE SCV SSC distinguished lecturer seminar on Thursday March 16, 2017 by Prof. Tom Lee, Stanford University with the title:

“Silicon is the New Steel: Building the Internet of Everything — The World’s First Terascale Network” 

Date: March 16, 2017 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk

Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, Directions.


Steel transformed civilization in the 20th century, shifting from high-tech material to commodity in the process. Silicon is undergoing an analogous transition, as the action shifts from circuits to systems. This talk will argue that multiple convergent trends are pushing us toward the terascale age, presenting us with both historic opportunities and historic challenges. The latter extend from DC to the millimeter wave, and from design tools to the economics of test. Securing a network possessing an “attack surface” of unprecedented magnitude, as well as supplying power to a trillion devices, remain challenges as well. Solving these problems will complete the transition of silicon from mere ubiquity to invisibility (the true mark of success).


Thomas Lee received his degrees from MIT where his 1989 thesis described the world’s first CMOS radio. He has been at Stanford University since 1994, having previously worked at Analog Devices, Rambus and other companies. He’s helped design PLLs for several microprocessors (notably AMD’s K6-K7-K8 and DEC’s StrongARM), and has founded or cofounded several companies, including the first 3D memory company, Matrix Semiconductor (acquired by Sandisk), and IoE companies ZeroG Wireless (acquired by Microchip) and Ayla Networks. He is an IEEE and Packard Foundation Fellow, has won “Best Paper” awards at CICC and ISSCC, was awarded the 2011 Ho-Am Prize in Engineering, as well as an honorary doctorate from the University of Waterloo. He is a past Director of DARPA’s Microsystems Technology Office, holds 70 patents, and owns about 200 oscilloscopes, thousands of vacuum tubes, and kilograms of obsolete semiconductors. No one, including himself, quite knows why.

Registration Link:

“Deep Learning in Siri” by Dr. Alex Acero, Apple

Date: March 23rd, 2017

IEEE Santa Clara Valley Circuits and Systems Society proudly co-sponsors the upcoming seminar of the Signal Processing chapter on Thursday, March 23, 2017 by Dr. Alex Acero, Apple with the title:

“Deep Learning in Siri”


AMD Commons Auditorium, 991 Stewart Dr., Sunnyvale, CA (map or Google Maps)


Need visitor registration to enter this facility. Please register here.



6:30pm: Check-in/Networking

7:00pm: Announcements

7:05pm: Presentation

8:15pm: Adjourn



FREE for IEEE members

$5 for Others


Siri, Apple’s personal assistant, first shipped in 2011 as part of iOS and brought conversational agents into the mainstream. Users can access Siri from their iPhone, iPad, Apple Watch, AppleTV and Carplay in 21 languages. Deep learning has revolutionized the field of machine learning, making a big impact in both core algorithms and application areas like speech recognition, critical for Siri. Mixture Density Networks, a particular type of deep learning, now power Apple’s TTS engine, making Siri’s voices more natural, smoother, and allowing Siri’s personality to shine through. Accented speech, always a challenge for speech recognition systems, can be addressed by training deep neural networks and convolutional neural networks with various sources of data properly weighted in order to achieve a robust acoustic model.



Alex Acero leads the speech team in Siri, Apple’s personal assistant for iPhone, iPad, Apple Watch, Apple TV, and Carplay. Before joining Apple in 2013, he spent twenty years with Microsoft Research, managing teams in Speech, Natural Language Processing, Information Retrieval, Multimedia, Communication and Computer Vision. His team at Microsoft Research built Bing Translator, and contributed to Xbox Kinect. From 1991-1993 he managed the speech team for Spain’s Telefonica. He has been granted 154 US patents.

Dr. Acero is IEEE Fellow and ISCA Fellow. He received the 2012 IEEE Signal Processing Society Best Paper Award for the paper “Context-dependent pre-trained deep neural networks for large-vocabulary speech recognition” for pioneering the use of deep learning in large vocabulary speech recognition. Alex is co-author of the textbook “Spoken Language Processing” and over 250 technical papers, with an h-index of 61 according to Google Scholar. Dr. Acero is Affiliate Faculty at the University of Washington. Alex received an engineering degree from the Polytechnic University of Madrid, a Masters from Rice University, and a PhD from Carnegie Mellon.

Dr. Acero is a member of IEEE Board of Directors. He has served in many roles within the IEEE Signal Processing Society, including President, Director Industrial Relations, Vice President Technical Directions, Member-at-Large of the Board of Governors, Chair of the Speech Technical Committee, Associate Editor for IEEE Transactions Speech and Audio Processing and IEEE Signal Processing Letters, member of the Editorial Board of IEEE Signal Processing Magazine and IEEE Journal on Selected Topics in Signal Processing, Publications Chair for ICASSP98.

Registration link for this event is

“On the Relationship between Nyquist Rate and Healthcare: Silicon Systems to Close the Sub-Sampling Gap in Health Screening and Monitoring” by Prof. Amin Arbabian, Stanford University

Date: April 20th, 2017

IEEE SCV CAS proudly co-sponsors the IEEE Santa Clara Valley Solid States Circuits Society upcoming technical talk on Thursday April 20, 2017 by Prof. Amin Arbabian, Stanford University with the title of:

“On the Relationship between Nyquist Rate and Healthcare:  Silicon Systems to Close the Sub-Sampling Gap in Health Screening and Monitoring”



Advances in healthcare technologies have mainly focused on therapeutics, interventional procedures, and diagnostics. These treatment steps have undergone significant improvements, leading to higher survival rates and enhancements in quality of life. Nevertheless, current trends are unsustainable due to inefficiency in addressing specific critical diseases and skyrocketing national healthcare costs. An important example is cancer, where mortality rates have not seen major improvements, even with the tremendous technological advances in diagnostic imaging tools over the last four decades.


Preventive screening and continuous monitoring have the potential to completely change the landscape in the war against cancer and other complex disease states. Today, the human body is monitored/screened infrequently, in contrast with advanced electronic systems (many of which our community designs and ships), which are routinely and frequently monitored and calibrated.  At best, patients only receive annual checkups with extremely low ‘resolution’. How do we bring new screening and monitoring technologies closer to the patients (i.e., consumers)? This talk summarizes our work in this general space, from new directions in low-cost, portable, and semiconductor-based, RF-Ultrasound hybrid “Tricorder” imaging systems, to ultrasound-powered implantable devices that can measure, detect, and act upon local physiological changes through closed-loop neuromodulation or “electroceuticals.” I will also briefly discuss our investigation of a noninvasive method of neuromodulation based on ultrasonic excitation.


Amin Arbabian received his Ph.D. degree in EECS from UC Berkeley in 2011 and in 2012 joined Stanford University, as an Assistant Professor of Electrical Engineering, where he is also a School of Engineering Frederick E. Terman Fellow. His research interests are in high-frequency circuits and systems, medical imaging and screening technologies, and ultra-low power sensors and implantable devices. Prof. Arbabian currently serves as an associate editor of the new IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology (J-ERM) and on the technical program committees for RFIC and ESSCIRC. He is the recipient or co-recipient of the 2016 Stanford University Tau Beta Pi Award for Excellence in Undergraduate Teaching, 2015 NSF CAREER award, 2014 DARPA Young Faculty Award (YFA) including the Director’s Fellowship, 2013 Hellman faculty scholarship, and best paper awards from several conferences including ISSCC (2010), VLSI Circuits (2014), RFIC symposium (2008 and 2011), ICUWB (2013), PIERS (2015), and the MTT-S BioWireless symposium (2016).

Registration Link:


Date: April 20, 2017 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk


Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, Directions.

“Time-Based Circuits – not just the Single Slope!” by Dr. Matt Straayer from Maxim Integrated Inc.

Date: May 18th, 2017

IEEE SCV CAS proudly co-sponsors the IEEE Santa Clara Valley Solid States Circuits Society upcoming technical talk on Part I of two-part seminars on Time-Based Circuits on Thursday May 18, 2017 by Dr. Matt Straayer from Maxim Integrated Inc. The title of the talk will be on:

“Time-Based Circuits – not just the Single Slope!”



Compared to circuits utilizing voltage or current to convey analog signals, time-based circuits offer unique attributes, ranging from simple, area efficient quantization to more complex techniques for time-based processing such as integration, interpolation, and noise shaping. Although time-based circuits are not new, the availability of fast, low-power transistors in advanced process nodes, combined with the challenges of traditional analog design techniques, has renewed interest in time as a signal domain both in academia and in industry. This talk will look at some obvious and more subtle differences between voltage and time-based circuits, and discuss tradeoffs in the context of application requirements. A few advanced state-of-the-art time-based circuits will motivate the audience to consider how time-based circuits can be a useful tool for their own designs.



Matt Straayer studied electrical engineering at University of Michigan and MIT. Currently he is Executive Director, Advanced Research and Development at Maxim, where his group develops architectures and enabling IP for a wide range of products and applications. His experiences include MEMS, RF, frequency generation, data converters, and power, and has found a valuable role for time-based circuits in each of these areas.


Registration Link:

Part II seminar by Prof. Pavan Hanumolu, UIUC, on August 17 is also available on registration page.

Date: May 18, 2017 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk

Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, DirectionsandMap

“Energy Efficient memory design for the compute continuum and beyond” by Dr. Jaydeep Kulkarni, Staff Research Scientist at Intel Corporation

Date: May 22nd, 2017

IEEE SCV CAS proudly sponsors the upcoming technical talk on Monday, May 22, 2017 by Dr. Jaydeep Kulkarni, Staff Research Scientist at Intel Corporation with the title of

“Energy Efficient memory design for the compute continuum and beyond” 



With the rapid advances in computing systems spanning from billions of IoTs (Internet of Things) to high performance exascale supercomputers, energy efficient design is an absolute must. Moreover, with the emergence of neural network accelerators for machine learning applications, there is a growing need for large capacity memories. It is estimated that by 2040, around 1 Trillion internet connected devices will be deployed generating millions of Zettabytes (1 Zetta = 10 21 ) consuming tens of Zetta-joules of compute energy/year. These trends clearly indicate the paramount importance of energy efficient memories across the compute continuum and to cater storage needs for future workloads.

In this seminar, I will discuss the circuit solutions for realizing energy efficient memory arrays. Supply voltage scaling is the primary driver to reduce energy consumption. The minimum operating supply voltage (Vmin) of a compute block consisting of static CMOS datapath logic and memory arrays is typically limited by process variations in the memory bitcells using minimum sized transistors. I will present an overview of low power memory design using novel bitcell topologies, Vmin-assist techniques, high density array designs, and adaptive and resilient design for reducing V/F guardbands.

I will conclude the seminar with by highlighting the importance of memories on the next generation computing systems and how cross-layer interactions across the hardware stack harnessing the benefits of each of its components are required to realize future energy efficient systems for the data centric world.

Bio for Dr. Jaydeep Kulkarni:

Dr. Jaydeep Kulkarni is a Staff Research Scientist at Intel Corporation. He received the Bachelor of Engineering (B.E.) degree from the University of Pune, India in 2002, the Master of Technology (M. Tech.) degree from the Indian Institute of Science (IISc) Bangalore, India in 2004 and Ph.D. degree from Purdue University, West Lafayette, IN, in 2009 all in electrical engineering. During 2004-05, he worked as a Design Engineer at Cypress Semiconductors, Bangalore and designed I/O circuits for micro-power SRAMs. He joined Circuit Research Lab (CRL) at Intel Corporation, Hillsboro, OR in 2009, where he is currently working as a staff research scientist. His research is focused on energy efficient integrated circuits and systems, emerging nanotechnologies, and alternative computing models. He has filed 30 patents, published 2 book chapters and 55 papers in referred journals and conferences.

Dr. Kulkarni received 2004 best graduate student award from IISc Bangalore, two Semiconductor Research Corporation’s (SRC) inventor recognition awards, 2008 ISLPED design contest award, 2008 Intel foundation Ph.D. fellowship award, 2008 SRC TECHCON best paper in session award, 2010 Purdue school of ECE outstanding doctoral dissertation award, three Intel patent recognition awards, seven Intel divisional recognition awards for successful technology transfers, 2015 IEEE Transactions on VLSI systems best paper award, and 2015 SRC outstanding industrial liaison award. He has participated in technical program committees of A-SSCC, ISLPED, ISCAS, and ASQED conferences. He is serving as a technical program co-chair for 2017 ISLPED, an associate editor for IEEE Transactions on VLSI Systems, and as an industrial liaison for SRC, NSF, Stanford System-X alliance, Stanford-NMTRI and STARnet research programs. He is a senior member of IEEE.


6:30pm: Networking/Light Dinner
7:00pm: Announcement
7:05pm: Presentation
8:15pm: Adjourn

Where: Qualcomm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Registration Link:

Registration Cost: Free. Food donation accepted: $2 for IEEE member, $5 for non-IEEE member



“Channel Selection at RF” by Prof. Behzad Razavi from University of California, Los Angeles

Date: June 15th, 2017

IEEE SCV CAS proudly sponsors the IEEE Santa Clara Valley Solid State Circuits Society upcoming technical talk on Thursday June 15, 2017 by Prof. Behzad Razavi from University of California, Los Angeles with the title of

“Channel Selection at RF”


A holy grail in RF design has been to perform channel selection at RF, i.e., remove strong interferers and even out-of-channel noise at the receiver input rather than in the baseband. Such an approach is attractive for it obviates the need for SAW filters and greatly relaxes the linearity requirements of the receiver chain, ultimately leading to a lower power consumption and a more compact design.

This research demonstrates a universal CMOS receiver employing RF channel selection and meeting the exacting demands of GSM and WCDMA. Drawing upon commutated networks, we introduce the concept of the “Miller bandpass filter” and several of its variants so as to create a receiver that achieves a narrow channel bandwidth and can withstand large blockers. Realized in 65-nm technology, the prototype provides a programmable bandwidth from 350 kHz to 20 MHz and draws 20 mW. The noise figure is 2.9 dB in the absence of blockers and 5 dB with a 0-dBm blocker at 20-MHz offset.



Behzad Razavi is Professor of Electrical Engineeirng at UCLA, where he conducts research on analog and RF integrated circuits. An IEEE Fellow, Prof. Razavi has served as an IEEE Distinguished Lecturer and has published more than 180 papers and seven books. He has received eight IEEE best paper awards and four teaching awards, and his books have been published in seven languages.

He received the 2012 IEEE Pederson Award in Solid-State Circuits and was recognized as one of the top ten authors in the 50-year history of the IEEE International Solid-State Circuits Conference. He is a member of the National Academy of Engineering and the recipient of the 2017 IEEE CAS John Choma Education Award.

Registration Link:

Date: June 15, 2017 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk

Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, Directions and Map (to locate Building E)

“System Level ESD: A New Focus” by Dr. Charvaka Duvvury, ESD Consulting

Date: July 11th, 2017

IEEE SCV CAS proudly sponsors the IEEE SCV-SF Electron Devices Society Seminar upcoming technical talk on Tuesday, July 11, 2017 by Dr. Charvaka Duvvury, ESD Consulting with the title of:

“System Level ESD: A New Focus”


With the continued scaling of technologies the ESD qualification has become a major challenge. This is mainly due to the demand for higher speed circuits, mostly implemented in large high pin count packages, and increased SoC applications. It has already been established that these are having consequences for ESD qualification requiring a new thrust to change the component ESD target levels. At the same time system level ESD has become much more important and combining with the new lower ESD target levels system protection is demanding a more thorough understanding with a co-design approach. This is especially the case for USB and HDMI interfaces along with RF applications. This seminar will give a brief roadmap for component level ESD levels followed by an overview of the system level ESD protection challenges. The concept of “system-efficient-ESD-design” (SEED) will be presented to describe a more desirable approach to achieve robust systems while preserving signal integrity. Examples of designing with simulation approaches for both hard and soft ESD failures will be introduced.


Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group. Charvaka is also a life fellow of the IEEE. He is currently working as a technical consultant on ESD design methods and ESD qualification support. Charvaka received his PhD in engineering science from the University of Toledo. He has published over 150 papers in technical journals and conferences and holds more than 75 patents. He is a recipient of the IEEE EDS Education Award (2013), Outstanding Contributions Award from the EOS/ESD Symposium (1990), Outstanding Industry Liaison Award twice from the Semiconductor Research Council (1994 and 2012), and IRPS Outstanding Paper Award as well as several Best Paper Awards from the ESD Symposium. He has been a Board of Director of the ESD Association since 1997. Charvaka also served in the Technical Program Committees of both IEDM and IRPS. He was a contributing editor for the IEEE Transactions on Device and Materials Reliability (TDMR) from 2001-2011. He is a co-founder and has been co-chair of the Industry Council on ESD Target Levels since 2006.

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

Date: Tuesday, July 11th, 2017

Time: 6:00 PM – 6:15 PM: Networking with food and refreshments

6:15 – 7:00 PM: Seminar 

Cost: Free

Location: Texas Instruments Building E Conference Center
2900 Semiconductor Dr., Santa Clara, CA 95052.
See the TI Building location map and directions

“Time-Based Circuits, Part II – Applications of time-based circuits in data conversion, filtering, and control” by Prof. Pavan Hanumolu, University of Illinois, Urbana-Champaign

Date: August 17th, 2017

IEEE SCV CAS proudly co-sponsors the IEEE Santa Clara Valley Solid State Circuits Society presentation on Thursday, August 17, 2017 by Prof. Pavan Hanumolu, University of Illinois, Urbana-Champaignof Part II of Distinguished Lecturer seminar series on Time-Based Circuits with the title of:

“Time-Based Circuits, Part II – Applications of time-based circuits in data conversion, filtering, and control”



In the 2nd part of this 2-part series on time-based circuits, I will present time-based signal representation as an alternative to classical voltage or charge-based signal representations. I will then show how this representation enables the implementation of fundamental building blocks such as integrators using mostly digital circuits. Finally, I will present case studies of time-based analog filters, analog to digital converters, and DC-DC converters to highlight the advantages, opportunities, and drawbacks of the time-based approach.



Pavan Kumar Hanumolu is currently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Illinois, Urbana-Champaign. He received the Ph.D. degree from the School of Electrical Engineering and Computer Science at Oregon State University, in 2006, where he subsequently served as a faculty member till 2013. Dr. Hanumolu’s research interests are in energy-efficient integrated circuit implementation of analog and digital signal processing, sensor interfaces, wireline communication systems, and power conversion.

Registration Link:

Date: August 17, 2017 (Thursday)
, Networking and refreshments
6:30-8:00pm, Technical Talk

Where: Texas Instruments Auditorium (Building E Visitor Center), 2900 Semiconductor Dr, Santa Clara, CA 95051, Directions and Map (to locate Building E)

“Special Session on Deep Learning” by C.-C. Jay Kuo, George Toderici, Shao-Yi Chien, Yulia Tell

Date: September 27th, 2017

IEEE SCV CAS proudly co-sponsors the Bay Area Multimedia Forum (BAMMF) upcoming talk on Wednesday, September 27, 2017 by two professors and two industry experts with the title of:

“Special Session on Deep Learning”

The speakers are

C.-C. Jay Kuo, Professor, University of Southern California
George Toderici, Staff Software Engineer, Google Research
Shao-Yi Chien, Professor, National Taiwan University
Yulia Tell, Technical Program Manager, Intel Corporation




“Why Deep Learning Networks Work So Well?” by C.-C. Jay Kuo, Professor, University of Southern California 

Deep learning networks, including convolution and recurrent neural networks (CNN and RNN), provide a powerful tool for image, video and speech processing and understanding nowadays. However, their superior performance has not been well understood. In this talk, I will unveil the myth of the superior performance of CNNs. To begin with, I will describe network architectural evolution in three generations: first, the McClulloch and Pitts (M-P) neuron model and simple networks (1940-1980); second, the artificial neural network (ANN) (1980-2000); and, third, the modern CNN (2000-Present). The differences between these three generations will be clearly explained. Next, theoretical foundations of CNNs have been studied from the approximation, the optimization and the signal representation viewpoints, and I will present main results from the signal processing viewpoints. I will use an intuitive way to explain the complicated operations of the CNN systems.


Dr. C.-C. Jay Kuo received his Ph.D. degree from the Massachusetts Institute of Technology in 1987. He is now with the University of Southern California (USC) as Director of the Media Communications Laboratory and Dean’s Professor in Electrical Engineering-Systems. His research interests are in the areas of digital media processing, compression, communication and networking technologies.
Dr. Kuo was the Editor-in-Chief for the IEEE Trans. on Information Forensics and Security in 2012-2014. He was the Editor-in-Chief for the Journal of Visual Communication and Image Representation in 1997-2011, and served as Editor for 10 other international journals.
Dr. Kuo received the 1992 National Science Foundation Young Investigator (NYI) Award, the 1993 National Science Foundation Presidential Faculty Fellow (PFF) Award, the 2010 Electronic Imaging Scientist of the Year Award, the 2010-11 Fulbright-Nokia Distinguished Chair in Information and Communications Technologies, the 2011 Pan Wen-Yuan Outstanding Research Award, the 2014 USC Northrop Grumman Excellence in Teaching Award, the 2016 USC Associates Award for Excellence in Teaching, the 2016 IEEE Computer Society Taylor L. Booth Education Award, the 2016 IEEE Circuits and Systems Society John Choma Education Award, the 2016 IS&T Raymond C. Bowman Award, and the 2017 IEEE Leon K. Kirchmayer Graduate Teaching Award.
Dr. Kuo is a Fellow of AAAS, IEEE and SPIE. He has guided 140 students to their Ph.D. degrees and supervised 25 postdoctoral research fellows. Dr. Kuo is a co-author of about 250 journal papers, 900 conference papers and 14 books.


“Recent Deep Learning Advances in Video Action Recognition” by George Toderici, Staff Software Engineer, Google Research

The field of action recognition has been traditionally dominated by “classical” methods, which rely on hand-crafted features that are extracted from the video frames, and then are fed into classification systems (such as linear classifiers or more complicated approaches). Recently, due to the increasing interest in, and feasibility of deep networks, a lot of research has concentrated on how to apply deep networks to this task. In this talk I will give an overview of a “generic” framework for action recognition using deep networks, discuss various frame-level approaches which may be integrated into this framework, and finally review the most recent advances in using motion as an additional feature.


George Toderici received his Ph.D. in Computer Science from the University of Houston in 2007 where his research focused on 2D-to-3D face recognition, and joined Google in 2008. His current work at Google Research is focused on lossy multimedia compression using neural networks. His past projects at Google include the design of neural-network architectures and classical approaches for video classification, action recognition, YouTube channel recommendations, and video enhancement. He has helped organize the THUMOS-2014 and YouTube-8M (2017) video classification challenges, and contributed to the design of the Sports-1M dataset. He has also served as Area Chair for the ACM Multimedia Conference in 2014, and is a regular reviewer for CVPR, ICCV, and NIPS.


“Quantized Convolutional Neural Network for Efficient Hardware Realization” by Shao-Yi Chien, Professor, National Taiwan University 

Convolutional neural networks (CNNs) have emerged to provide powerful discriminative capability, especially in the world of image recognition and object detection. However, their massive computation requirements, storage and memory accesses make them hard to be deployed on mobile or embedded systems. In this talk, several optimization schemes for Convolutional neural networks (CNNs) will be first reviewed. Among them, quantization technique is emphasized since it can benefit many kinds of computing architectures. A dedicated hardware architecture design for face detection will also be shown as an example.


Shao-Yi Chien received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, Taiwan, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan County, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. Since 2012, he has been a Professor. Dr. Chien is the Associate Chair of Department of Electrical Engineering of National Taiwan University from 2013 to 2016. From 2017, he is a visiting professor in Intel Lab. His research interests include video analysis, computer vision, perceptual coding technology, image processing for digital still cameras and display devices, computer graphics, and the associated VLSI and processor architectures.

Dr. Chien served as an Associate Editor for IEEE Transactions on Circuits and Systems for Video Technology, IEEE Transactions on Circuits and Systems I: Regular Papers, and Springer Circuits, Systems and Signal Processing (CSSP). He also served as a Guest Editor for Springer Journal of Signal Processing Systems in 2008. He also serves on the technical program committees of several conferences, such as ISCAS, ICME, SiPS, A-SSCC, and VLSI-DAT.


“Deep Learning at Scale with Apache Spark” by Yulia Tell, Technical Program Manager, Intel Corporation 

Deep learning is a fast growing subset of machine learning. There is an emerging trend to conduct deep learning in the same cluster along with existing data processing pipelines to support feature engineering and traditional machine learning. Being one of early and top contributors to Apache Spark, Intel has developed and open sourced a distributed deep learning framework called BigDL that is built organically on big data (Apache Spark) platform. It combines the benefits of high performance computing and big data architecture for rich deep learning support.

In this session, I will introduce BigDL, cover how our customers use BigDL to build end-to-end ML/DL applications, talk about platforms on which BigDL is deployed and also provide an update on the latest improvements in BigDL. BigDL helps make deep learning more accessible to the Big Data community, by allowing them to continue the use of familiar tools and infrastructure to build deep learning applications. With BigDL, users can write their deep learning applications as standard Spark programs, which can then directly run on top of existing Spark or Hadoop clusters. BigDL on Spark also enables customers to eliminate large volume of unnecessary dataset transfer between separate systems, eliminate separate HW clusters and move towards a CPU cluster, reduce system complexity and the latency for end-to-end learning.


Yulia Tell is a Technical Program Manager in Big Data Technologies team within Software and Services Group at Intel. She is working on several open source projects and partner engagements in the big data domain. Her work is focused specifically on Apache Hadoop and Apache Spark, including big data analytics applications that use machine learning and deep learning. She has worked in several groups at Intel over the past 10 years, including work on Intel’s HPC software tools and services. Yulia also is a training committee lead of Women in Big Data on the West Coast. Women in Big Data is a grass-roots community focused on strengthening the diversity in big data and analytics and aims to champion the success of women in big data domain. Yulia has received her MSc degree in Computer Science from Moscow Power Engineering Technical University. She has also completed executive education program on Market Driving Strategies at London Business School.

Registration Link:

Date: September 27, 2017 (Wednesday)
Time: 1:30-4:30pm

Where: Intel SC-12 Auditorium, 3600 Juliette Lane, Santa Clara, CA 95054 


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