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2014 Events

Terabit Optical Systems

Date: January 27th, 2014

Speaker: Mr. Thé Linh Nguyen, Finisar Corporation

Presentation available to download here: pdf



Optical transmission and interconnects have become the preferred choice for any distances from ultra long haul of >2000 km in the telecom applications to short reaches of 100m in the datacom applications. In a few years as bandwidth requirement increases optics will be widely used in distances of a few meters in the intra-rack down to a few centimeters in the intra-board communications. Ultimately intra-chip communications could use optics as well. This seminar examines industry developments that are driving towards terabit/s optical links. These developments are driven by different economic and technical requirements depending on the applications, mainly telecom transport, datacom and high-performance computing. These requirements drive technology, architecture and design choices, standardizations and multi-source agreements. This seminar is intended ideally for ICs and systems designers outside of the optical communication field to get a comprehensive picture of the current solutions and the developing trends in the industry. The seminar is organized according to three general applications: telecom, datacom and parallel optics. It dives into some of the pertinent theories of the optical medium and optical components, end-user requirements and how they affect circuit and technology choices for each of the applications.

Thé Linh Nguyen received the B.S. and a M.S. from University of Waterloo, Canada in 1993 and the M.S. from Queen’s University, Canada in 1995 both in Electrical Engineering. For his M.S. thesis he successfully designed of a low-noise balanced optical receiver IC optimized for Continuous-Phase Frequency-Shift Keying (CPFSK) systems working at 10Gb/s using 1um GaAs MESFET technology with 20GHz Ft.
He spent 6 years at Nortel Networks, Ottawa Canada where he was part of a team that designed the world’s first OC-192 and OC-768 systems. He worked on the designs of 10Gb/s AGC module, 10Gb/s modulator driver IC and 40Gb/s TIA IC. He has been with Finisar Corporation since 1999 where he has been working on laser and modulator driver, post amplifier, CDR and SerDes ICs for bit rates up to 40Gb/s. He holds 33 issued and pending patents in the field of IC design and optical communications. He authored and co-authored 5 papers on the subject of IC designs for optical and wireless communications. He is currently a Senior Manager of IC Development at Finisar.
From 2000 to 2003 he served on the Technical Committee on High-Speed Digital and Mixed Signal ICs for the GaAs IC Symposium, currently called Compound Semiconductor IC Symposium, where he was also the committee chair for two years. He is currently serving on the Technical Program Committee on Optical Interconnection Networks for Datacom and Computercom for the 2014 OFC.

DSP: Whence It Came and Where It’s Going; A Tour for Non-Specialists

Date: March 17th, 2014

Event cosponsored by the IEEE Signal Processing Society – SCV Chapter


Speaker: Mr. Shiv Balakrishnan, Mobility Semiconductors

 Presentation available to download here: pdf


This is a review of the field of Digital Signal Processing (DSP) and is intended for those who do not necessarily use DSP on a daily basis. We look at the key drivers for the field such as FFT and Digital Filters and show how the evolution of these techniques served growing numbers of important application areas such as communications and multimedia.  The rise of programmable Digital Signal Processors (also known, somewhat confusingly, as DSP’s) is chronicled along with the differences between fixed point and floating point implementations. The impact of DSP on general purpose compute architectures is described, along with the growth in hardware implementations both in IC technology and FPGA. We also look at DSP as a market and see how that view has significantly fragmented by application area in recent times. The impact of DSP on analog design is touched upon as well as describing a number of newer application areas for DSP technology.

Shiv Balakrishnan received his BTech degree in EE from the Indian Institute of Technology, Kanpur. He got his Master’s degree in EE from the University of Florida where he designed Digital Filters for EEG Processing. He spent over a decade working at Tektronix where he was a key contributor to the design of high speed digitizing oscilloscopes. In Silicon Valley, he has worked both for large corporations such as Sun Microsystems and Philips Semiconductors, on products like the Sun Ray-1 thin client and TriMedia VLIW processor, as well as numerous start ups. Shiv is named co-inventor on multiple patents in signal processing. Currently he divides his time between RiverSilica, a Bangalore, India-based start up that makes video transcoders and Mobility Semiconductors, a start up in analog/mixed-signal design.


Presentations on 3D gesture recognition

Date: April 21st, 2014

co-sponsor with SSC

First Talk:

Speaker: Dr. Cyrus Bamji, Microsoft Corp.

A 512×424 CMOS 3D Time-of-Flight Image Sensor with Multi-Frequency Photo-Demodulation up to 130MHz and 2GS/s ADC

Paper and presentation available here. (IEEExplore Subscription required)


In this talk, the pixel and signal path of a 512×424-pixel ToF image sensor is presented. Consecutive frames with different modulation frequencies are combined, which enables a range error of less than 1% over ranges from 0.8 to 4.2m. Modulation frequencies up to 130MHz are supported, and the modulation contrast at 50MHz is 67%.


Cyrus Bamji received his SB, SM and PhD (1989) in EECS from MIT.  His early works were in the area of CAD where he won several best paper awards and wrote a book on hierarchical compaction techniques.  He is the inventor of over 40 patents most in the field of TOF.  He was the CTO and a co-founder of Canesta a TOF company acquired in 2010 by Microsoft.  He now develops next generation TOF technologies at Microsoft.

Second talk:

Speaker: Dr. Richard J. Pzybyla, Chirp Microsystems

Ultrasonic 3D Rangefinder on a Chip

Paper and presentation available here. (IEEExplore subscription required)


An ultrasonic 3D rangefinder system uses an array of AlN MEMS transducers and custom readout electronics to localize targets over a +/-45 degree field of view up to 1m away. The 0.18μm CMOS readout ASIC comprises 10 independent channels with separate high voltage transmitters, readout amplifiers, and ADCs. Power dissipation is 400μW at 30fps, and scales to 10μW/ch at 10fps.


Richard J. Przybyla received the B.S. degree in electrical engineering from Oregon State University in 2008. Last year, he received his Ph.D. in electrical engineering from Professor Bernhard Boser’s group at University of California, Berkeley. He is a co-founder of Chirp Microsystems, which is commercializing low-power ultrasonic sensor systems. Dr. Przybyla is interested in circuits and systems which interface to the physical world.

Terahertz and Millimeter-Wave Frequency Generation and Synthesis in Silicon

Date: May 29th, 2014

IEEE SCV CAS cosponsors IEEE SCV SSCS on a technical talk by Payam Heydari, UC Irvine on May 29, 2014

Time: Thursday, May 29, 2014, 6pm-8pm
Networking and snacks: 6:00pm-6:30pm
Technical Talk: 6:30-8:00pm
Where: Texas Instruments Building E Auditorium, 2900 Semiconductor dr., Santa Clara, CA 95051

(Registration is required, registration link:

Abstract: Terahertz (THz) and millimeter-wave (mm-wave) imaging and sensing is considered to be one of the emerging and disruptive technologies over the next decade. THz (including the W-band) waves pass through non-conducting materials such as clothes, paper, wood and brick and so cameras sensitive to them can peer inside envelopes, into living rooms and “frisk” people at distance. THz/mm-wave imaging/sensing systems, therefore, will be key enabling components in applications such as security surveillance (to find concealed weapons and explosives), non-destructive testing, biology, radio astronomy, multi-gigabit wireless connectivity, and medical imaging. One of the most critical and daunting tasks in a THz/mm-wave system is signal generation and frequency synthesis. This lecture presents a comprehensive overview and comparative study of research efforts which have explored several circuit techniques and architectures leading to highly efficient frequency synthesis and signal generation in silicon.

Bio: Payam Heydari received his B.S. and M.S. degrees (Honors) in Electrical Engineering from Sharif University of Technology in 1992 and 1995, respectively and Ph.D. degree from the University of Southern California in 2001. He is currently a Professor of Electrical Engineering and director of the Nanoscale Communication IC (NCIC) Lab at the University of California, Irvine. His research covers the design of terahertz/millimeter-wave/RF and analog integrated circuits. He is the (co)-author of two books, one book chapter, and more than 110 journal and conference papers. Prof. Heydari is the Distinguished Lecturer of IEEE Solid-State Circuits Society. He has served on the Technical Program of International Solid-State Circuits Conference (ISSCC) and as the Guest Editor of IEEE Journal of Solid-State Circuits (JSSC), and Associate Editor of IEEE Trans. on Circuits and Systems – I as well as many other conferences and journals on integrated circuit design.

Digital Delta-Sigma Modulators

Date: July 28th, 2014

Michael Peter Kennedy
Professor of Microelectronic Engineering
University of College Cork

Presentation available here: pdf
Video recording of the talk available here



Although Digital Delta-Sigma Modulators (DDSMs) are more widely employed
commercially than analog DSMs, they are less studied. In particular,
issues such as spur generation are not well understood. In the past
decade, much progress has been made in this field. This presentation gives
a brief introduction to DDSMs for non-specialists, providing insights into
the unusual behavior which is often observed in applications. By
understanding the root cause of the behavior, novel solutions have been
developed to eliminate many of the problems—such as spurs and idle
tones—which have historically plagued applications containing DDSMs.
Furthermore, by understanding the role of the DDSM in a complete signal
processing chain, we show how the concepts of error-masking and
bus-splitting can be used in novel architectures to reduce the hardware
complexity or to increase throughput.


Michael Peter Kennedy is Professor of Microelectronic Engineering at
University College Cork (UCC). He received the BE (Electronics) degree
from UCD in 1984, the MS and PhD from the University of California at
Berkeley in 1987 and 1991, respectively, and the DEng from the National
University of Ireland in 2010. He joined UCC as Chair of the Department of
Microelectronic Engineering in 2000. He served as Dean of the Faculty of
Engineering from 2003 through 2005 and as Vice-President for Research from
2005 to 2011.

He has over 340 research publications (including four patents) in the
fields of oscillator design, hysteresis, neural networks, nonlinear
dynamics, chaos communication, mixed-signal test, and frequency synthesis.
He has worked as a consultant for SMEs and multinationals in the
microelectronics industry and is founding Director of the Microelectronics
Industry Design Association (MIDAS Ireland) and the Microelectronic
Circuits Centre of Ireland (MCCI).

He was made a Fellow of the Institute of Electrical and Electronic
Engineers (IEEE) in 1998 for contributions to the theory of neural
networks and nonlinear dynamics and for leadership in nonlinear circuits
research and education. He has received many prestigious awards including
Best Paper (International Journal of Circuit Theory and Applications), the
88th IEE Kelvin Lecture, IEEE Millenium and Golden Jubilee Medals, the
inaugural Royal Irish Academy Parsons Award in Engineering Sciences, and
the IEEE Solid-State Circuits Society Chapter of the Year Award 2010. In
2004, he was elected to membership of the Royal Irish Academy and was
made a Fellow of the Institution of Engineers of Ireland by Presidential
Invitation. He was made a Fellow of the Irish Academy of Engineering in

From 2005 to 2007, he was President of the European Circuits Society and
Vice-President of the IEEE Circuits and Systems (CAS) Society (with
responsibility for Europe, Africa and the Middle East). During 2012 and
2013, he was a Distinguished Lecturer of the IEEE CAS Society. He has been
Secretary for International Relations of the Royal Irish Academy since
2012. He is currently chair of the PE7 Starter Grants Panel at the
European Research Council.

IEEE Tutorial on LDPC Decoding: VLSI Architectures and Implementations

Date: August 6th, 2014

When: Wednesday, August 6, 2014 from 7:00 PM to 9:30 PM (PDT)

Where: 5001 Great America Parkway, Santa Clara, CA 95054

Event co-sponsored by: IEEE-SCV-PACE, SPS, ITS, CAS, SSC, ComSoc and Magnetics society


LDPC codes are now being used in Hard disk drive read channels, Wireless (IEEE 802.11n/ IEEE 802.11ac, IEEE 802.16e WiMax), 10-GB, DVB-S2, and more recently in Flash SSD. Tutorial’s target audience is system engineers and design engineers. Tutorial has two parts, first module is focused on LDPC Decoding and second module is focused on VLSI Architectures and Implementations. IEEE Standard draft LDPC codes for Flash memories also will be covered.

Tutorial overview

Module 1 LDPC Decoding

1.1) LDPC codes

1.2) Hard decision decoding,

1.3) LLR basics and LLR generation for soft decoding for Flash memory channel

1.4) Soft decoding and Min-Sum Algorithm

1.5) LDPC decoder performance characteristics, trapping sets and error floor

1.6) Basics of Code Structures for Efficient hardware.

Module 2 VLSI Architectures and Implementations

2.1) Check Node Unit Design and Value-reuse property

2.2)   Non-layered decoder architecture

a)   Block serial processing

b)  Translating throughput requirement to H matrix parameters and edge parallelization

2.3)  Layered decoder architecture

 a) Block serial processing

 b) Block serial processing for irregular H matrices, scheduling of decoder processing

 c) Block parallel processing

 d) Translating throughput requirement to H matrix parameters and edge parallelization

 e) Case study of decoders for IEEE P1890 Standards draft LDPC codes (P1890-Standards Working Group on Error Correction Coding for Non-Volatile Memories)

2.4) Error floor mitigation schemes



Module 1:

Ned Varnica, Marvell Semiconductor

Dr. Varnica’s presentation is available for download here:pdf

Ned Varnica received the B.S. degree in Electrical Engineering in 2000 from School of Electrical Engineering, University of Belgrade, Serbia, the M.S. degree in 2001 and Ph.D. in 2005 both from Harvard  University, Cambridge, Massachusetts. 

Since 2005 he has been with Marvell Semiconductor Inc, Santa Clara, California. He held short-term research positions at Maxtor Corporation, Shrewsbury, Massachusetts in 2002 and Lucent Bell Labs, Murray Hill, New Jersey in 2004. He spent the summer of 2003 as a visiting researcher at University of Hawaii at Manoa, Honolulu. His research interests are in the areas of communication theory, information theory, channel and source coding and their applications to digital data storage and wireless communications.

Dr. Varnica received the Best Student of the Class Award from the Department of Communications at the School of Electrical Engineering, University of Belgrade in 2000.  He is a co-recipient, with A. Kavcic and X. Ma, of the 2005 IEEE Best Paper Award in Signal Processing and Coding for Data Storage.


Module 2:

Kiran Gunnam, Violin Memory

Dr. Gunnam’s presentation is available for download here:pdf

Kiran Gunnam received the MSEE and PhD in Computer Engineering from Texas A&M University, College Station, TX. He currently works as Director of Engineering at Violin Memory.  He previously held research and development positions at Nvidia, Certicom, LSI, Marvell Semiconductor, Starvision Technologies, Schlumberger, Intel and Texas Engineering Experiment Station.

Dr. Gunnam has extensive research and development work experience in complex data path and control path systems. Dr. Gunnam is an expert in IC implementation of communications and signal processing systems. His PhD research contributed several key innovations in advanced error correction systems based on low-density parity- check codes (LDPC) and led to several industry designs. He has done extensive work on ASIC hardware architecture, micro-architecture and digital IC implementation for different systems (IEEE 802.11n Wi-Fi, IEEE 802.16e WiMax, IEEE 802.3 10-GB, Holographic read channel, HDD read channel and Flash read channel).

Dr. Gunnam has around 50 issued US patents and several pending patents and invention disclosures. He is the lead inventor/sole inventor for 90% of them. He is an IEEE Senior Member. He is also an IEEE Solid State Circuits Society Distinguished Lecturer for 2013 and 2014.

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