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Date: November 14th, 2019
Machine Learning (Signal Processing!) for Networked Systems

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Upcoming Events

The following schedule and location hold for most events, unless otherwise noted:

  • 6:30pm: Networking/Light Dinner
  • 7:00pm: Announcement
  • 7:05pm: Presentation
  • 8:15pm: Adjourn

Cost: Free. Food donation accepted: $2 for IEEE member, $5 for non-IEEE member.

Location: Cypress Semiconductor Corporation, Main Auditorium in Building 6, 198 Champion Ct, San Jose, CA 95134

We would appreciate suggestions for speakers to present at our meetings in the future.

Instructions for attending live broadcast events using the Zoom conference systems

 

We are proud to announce that the CASS Santa Clara Valley Chapter received 

the 2019 Regions 1-7 Chapter of the Year Award !

Machine Learning (Signal Processing!) for Networked Systems

Date: November 14th, 2019

Machine Learning (Signal Processing!) for Networked Systems

Co-sponsored event with Signal Processing Society

Lecture by John Apostolopoulos

VP/CTO Enterprise Networking, and Lab Director for Innovation Labs, Cisco

Event Sponsored and Organized By:

IEEE SPS Chapter of Santa Clara Valley

Co-Sponsors:

IEEE Computer Society

IEEE Information Theory Society

IEEE Communications Society

Circuits and Systems Society (CASS)of Santa Clara Valley

Registration Link: here.

Agenda:

6:30pm-7:00pm: Registration, Food, Networking

7:00pm-8:00pm: Talk

8:00pm-8:30pm: Q&A and Networking

Parking:

Please park in parking structure close to the building on Octavius Drive. First building after passing AMD and the road does a curve to the right. Please walk around AMD building to the Highway 101 side to the visitor entrance.

Cost:

Free

Donations accepted at the door.

Abstract:

It is an exciting time as machine learning (ML) techniques, based on signal processing (SP) and other disciplines, are enabling us to solve a wide range of challenging and valuable problems. In this talk I will share how we are applying ML to improve networked applications, such as interactive video communications and emerging multi-user AR/VR, and networked systems, such as Internet of Things (IoT) systems. A key theme in this talk is to show, via examples, how a modern network provides new sources of data that enables SP and ML experts to solve a diverse set of important problems.

This talk will examine how machine learning (ML) benefits networked systems by highlighting four examples. First, we will examine Intent-Based Networking (a modern architecture for designing and operating a network) and how ML can be used to increase visibility, diagnose problems and identify associated remedies, and provide assurance on application performance. Next, we’ll examine how to understand what devices are connected to the network, which is a key step to providing customized network performance and protecting those devices. In the context of ever-growing security threats, we’ll examine how ML can be applied to address the challenge of detecting malware sneaking in an encrypted flow without requiring decryption of those flows. Lastly, we’ll look at the move from today’s Cloud-based ML to the promising approach of Distributed ML across Edge and Cloud that can lead to improved scalability, reduced latency, and improved privacy for multimedia applications. It is noteworthy that while ML often raises privacy concerns, the last two examples showcase how an elegant application of ML can achieve the desired goal while preserving privacy.

Biography:

John Apostolopoulos is VP/CTO of Cisco’s Enterprise Networking Business (Cisco’s largest business) where his work includes wireless (from Wi-Fi 6 to 5G), Internet of Things, multimedia networking, visual analytics, and ML and AI applied to the aforementioned areas. Previously, John was Lab Director for the Mobile & Immersive Experience (MIX) Lab at HP Labs. The MIX Lab conducted research on novel mobile devices and sensing, mobile client/cloud multimedia computing, immersive environments, video & audio signal processing, computer vision & graphics, multimedia networking, glasses-free 3D, wireless, and user experience design. John is an IEEE Fellow, IEEE SPS Distinguished Lecturer, named “one of the world’s top 100 young innovators” by MIT Technology Review, contributed to the US Digital TV Standard (Engineering Emmy Award), and his work on media transcoding in the middle of a network while preserving end-to-end security (secure transcoding) was adopted in the JPSEC standard. He published over 100 papers, receiving 5 best paper awards, and about 80 granted US patents. John was a Consulting Associate Professor of EE at Stanford. He received his B.S., M.S., and Ph.D. from MIT.


Lecture by Dr. Sorin P. Voinigescu, “Towards Monolithic Quantum Computing Processors In Production FDSOI CMOS Technology”

Date: December 12th, 2019

“Towards Monolithic Quantum Computing Processors In Production FDSOI CMOS Technology”

Dr. Sorin P. Voinigescu, University of Toronto

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

Co-sponsors:

PROGRAM:

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Lecture will be broadcast live on Zoom and recorded. Please register to receive Zoom conference details one day before the event.

DATE:

Thursday, December 12th, 2019

REGISTRATION LINK:

Here

Abstract:

This presentation will discuss the fundamental concepts and the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology,. The beneficial aspects of the SiGe channel hole-spin qubit will be emphasized in comparison with its silicon-only electron-spin counterpart. It is also shown that, at 2 K, MOSFETs and cascodes can be operated as quantum dots in the subthreshold region, while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively. Challenges in the design and testing of quantum processor units monolithically integrated with readout and mm-wave spin control electronics in commercial 22nm FDSOI CMOS technology, will also be covered. Finally, I will present measurements for full technology characterization at cryogenic temperatures up to 67 GHz.

Bio:

Sorin P. Voinigescu is a Professor in the Electrical and Computer Engineering Department at the University of Toronto where he holds the Stanley Ho Chair in Microelectronics and is the Director of the VLSI Research Group. He is an IEEE Fellow and an expert on millimeter-wave and 100+Gb/s integrated circuits and atomic-scale semiconductor device technologies. He obtained his PhD degree in Electrical and Computer Engineering from the University of Toronto in 1994 and his M.Sc Degree in Electronics and Telecommunications from the Politechnical Institute of Bucharest in 1984.

Venue:

QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

Zoom Broadcast:

Lecture will be broadcast live on Zoom and recorded. Please register to receive Zoom conference details one day before the event.

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.



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