“Variation Robustness for Analog/Mixed-Signal, Custom Digital and Memory Design”

by Patrick G. Drennan, Solido Design Automation, Inc.

Abstract: Variation Robustness for Analog/Mixed-Signal, Custom Digital and Memory Design Patrick G. Drennan, Ph.D. Chief Technology Officer Solido Design Automation As process technologies and supply voltages shrink, designers are faced with a pressing need to address systematic and random sources of variation in a more deliberate and thorough way. Accounting for variation within the flow of design has not progressed commensurate with the process technologies. We still rely on best-, worst- case corners, mismatch plots and maybe a Monte Carlo verification if there is enough time. It is time for a new approach. This talk will begin with a brief review of the physical phenomena and industry standard device models for variation sources, including random local and global variations and systematic proximity effects. New techniques to accelerate, increase accuracy and derive more information from statistical variation analysis will be presented.

Bio: Patrick Drennan is Chief Technology Officer of Solido Design Automation, Inc. Prior to joining Solido, Patrick was a Distinguished Member of the Technical Staff at Freescale Semiconductor (formerly Motorola, Inc.). Patrick was one of the creators of the backwards propagation of variance (BPV) method for statistical characterization. This model guarantees consistency between simulation and silicon measurement and it is valid for all biases and geometries, which are significant attributes for design. His mismatch (local variation) model earned the Best Regular paper at the 2002 IEEE Custom Integrated Circuit Conference. He was the first to describe the impact of shallow trench isolation (STI) and well proximity effect (WPE) on design, demonstrating that the WPE produces a graded channel MOSFET. More importantly, he showed the catastrophic impact these unforeseen phenomena can have on circuit design. For this work, he received the Best Invited Paper at the 2006 IEEE Custom Integrated Circuit Conference. Patrick has extensive experience in measurement, modeling, characterization, test structure generation and design application of systematic and stochastic semiconductor variations. Patrick received the B.S. degree in microelectronic engineering and M.S. degree in electrical engineering from Rochester Institute of Technology and the Ph.D. degree in electrical engineering from Arizona State University.

“Simplified Fast Motion Estimation: Simplified and Unified Multi-Hexagon Search (SUMH) with Context Adaptive Lagrange Multiplier (CALM)”

by Prof. Nam Ling, IEEE Fellow & IEEE Distinguished Lecturer

Abstract: Fast motion estimations are especially important to speed up the time-consuming encoding processes for H.264 video encoding. In this talk, we first present our simplified fast motion estimation method, called Simplified and Unified Multi-Hexagon Search (SUMH), that produces a significant speed-up as compared with today’s fast motion estimations, yet encounters only a small PSNR degradation when compared to that of full search. In addition, we present a novel method to refine the Lagrange multiplier, called Context Adaptive Lagrange Multiplier (CALM), for rate-constrained motion estimation. Both our methods were recently adopted into the H.264/MPEG-4 AVC video coding international standard (including the text document and the JM reference software). Our SUMH is based on two principles, partial distortion search (PDS) and dual-halfway-stop (DHS) algorithms. PDS generally produces less video quality degradation of the predicted images than those of conventional fast block matching algorithms (BMAs). However, the speedup gain of PDS algorithms is usually limited. In this talk, we present an enhancement over a normalized PDS (NPDS) algorithm to further reduce block matching motion estimation complexity and improve video fidelity. The novelty of our algorithm is that, in addition to the halfway-stop technique in NPDS, a dual-halfway-stop (DHS) method, which is based on a dynamic threshold, is proposed so that block matching is not performed against all searching points. The dynamic threshold is obtained via a linear model utilizing already computed distortion statistics. An adaptive search range mechanism based on inter block distortion further constrains the searching process. Experimental results show that our proposed method reduces the encoding time by about 55% on the average when compared to those of the state-of-the-art methods, with similar rate-distortion performances. Our SUMH algorithm, making use of DHS-NPDS, consists of two parts, an integer-pel fast search and a sub-pel fast search. To extend motion estimation further, we propose a new simple and efficient method to adjust Lagrange multipliers based on the context (CALM), which improves the accuracy for the detection of true motion vectors as well as the most efficient encoding modes for luma, which are used for deriving the motion vectors and modes for chroma. Simulation results show that the chroma bit rates can be reduced by 4.36% and 4.80% (on the average) for U- and V- chroma components, respectively, when compared with that of the recent JM reference software. In addition, the coding efficiency improvement is comparable to the more complicated rate-distortion optimized (RDO) mode decision techniques.

Bio: Prof. Nam Ling received a B.Eng. degree in Electrical Engineering from the National University of Singapore (NUS). He received M.S. and Ph.D. degrees, both in Computer Engineering, from the University of Louisiana at Lafayette, U.S.A. Prof. Ling is currently a full Professor with the Department of Computer Engineering and the Associate Dean (Research and Faculty Development) for the School of Engineering at Santa Clara University (SCU), California, U.S.A. He is also a Consulting Professor to the National University of Singapore (NUS Overseas Colleges) and a Guest Professor of Shanghai Jiao Tong University (China). He has served as Visiting Professor/Consultant/Scientist/Scholar to institutions such as the Institute for Infocomm Research (I2R) (Singapore), Nanyang Technological University (Singapore), National Dong Hwa University (Taiwan), and National Chiao Tung University (Taiwan). Prof. Ling has more than 130 publications in the fields of video/image coding, video decoder design, video communications, and systolic arrays. He is the primary author of the book entitled Specification and Verification of Systolic Arrays. He and his team’s proposal on Simplified and Unified Multi-Hexagon Search (SUMH) (previously called simplified fast motion estimation or SFME) was adopted in 2005, and their Context Adaptive Lagrange Multiplier (CALM) method was adopted in 2006, both into the H.264/MPEG-4 AVC video coding international standard. Prof. Ling received the Arthur Vining Davis Junior Faculty Fellowship in 1991 and the SCU Outstanding Achievement Award in Teaching, Research, and Service, in 1992. Prof. Ling was named 1999 Researcher of the Year by SCU Engineering. He received the University Award for Recent Achievement in Scholarship in 2002, the SCU President’s Recognition Award in 2005, and the University Award for Sustained Excellence in Scholarship in 2007. He was named IEEE Distinguished Lecturer (Circuits and Systems) for 2002-2003 and 2007-2008. Prof. Ling also received the 2003 IEEE ICCE Best Paper Award (First Place Winner) for his work on MPEG-4 face animation. Prof. Ling became an IEEE Fellow effective January 2008 for contributions to video coding algorithms and architectures. Prof. Ling served as an Associate Editor for the IEEE Transactions on Circuits and Systems – I in 2002-03. He was a Guest Editor for the Journal of VLSI Signal Processing Systems special issue in 2006. In 1993 – 1995, Prof. Ling served as the Chair of the IEEE Computer Society Technical Committee (TC) on Microprocessors and Microcomputers. Currently, he serves as the Chair of the IEEE Circuits and Systems Society Circuits and Systems for Communications Technical Committee. He is also a member of the VSPC TC (IEEE Circuits and Systems Society) and a member of the DISPS TC (IEEE Signal Processing Society). Prof. Ling was the General Chair for the IEEE Hot Chips Symposium in 1995. He was Technical Program Co-Chair for ISCAS’07, SiPS’07, DCV’02, and SiPS’00. He was Track Co-Chair for ISCAS’04, ISCAS’05, and ISCAS’06. Prof. Ling served in program committees, organizing committees, and as session chairs for many IEEE conferences. He has delivered more than 80 invited/distinguished/keynote colloquia in eight different countries.

“Using Thermal Analysis as a Tool to Aid Analog Floorplanning”

by David Schwan, RFMD

Abstract: Todays’ IC designers are being driven to reduce area and increase performance and power-efficiency. Local circuit temperature can affect circuit performance, speed and current consumption, as well create reliability problems like electro-migration and thermal-runaway. Temperature can be an engineered parameter, like voltage current, or resistance; instead of the traditional “seat of the pants” guess-temics. Design can be done without impacting reliability or performance, by looking at thermal maps of the circuit, thus aiding the floor-planning process to reduce temperatures, allowing transistors to operate in potentially more usable regions or to reduce temperature deltas in sensitive areas of the design; this can translate to lower operating currents, meaning greater efficiency. Since electro-migration is a function of temperature, current densities in metal traces are typically derated at higher temperatures. Lowering the operating temperature can mean narrower power traces, potentially reducing interconnect parasitics, or improved reliability. The presentation will show results from using Gradient Design Automation’s CircuitFire to iterate placement of the transistors in a 1.9GHz 24dBM power amplifier, and the resulting effect on (predicted) operating temperature, and PA power efficiency.

Bio: David Schwan is a CAD and Layout Manager for RFMD and works in the Multi-Market Product group (formerly Sirenza Microdevices) . He is responsible for all tool support for the MPG division; which includes Analog, Digital, and RF tools; System level design, front end design, and back end design. He is the author of numerous papers in CAD methodology and IP. He has two patents pending. He is a member of the GSA (formerly FSA) mixed-signal subcommitte, and is an active participant in the GSA IP ecosystem.

“Implementation of a Third Generation 16 Core 32 Thread Chip-Multithreading SPARC Processor”

by Georgios K. Konstadinidis, SUN Microsystems

Abstract: This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16-cores with shared memory architecture and supports a total of 32 main Threads plus 32 Scout Threads. It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The 396mm2 chip, is fabricated in a 11M 65nm CMOS process and operates at a nominal frequency of 2.3GHz, consuming a maximum power of 250W at 1.2V This presentation provides a brief overview of the Architectural highlights followed by a more in depth discussion on the physical implementation aspects of this design. The focus is on the physical implementation challenges and solutions, including circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead.

Bio: Georgios K. Konstadinidis is a Distinguished Engineer at SUN Microsystems, focused on high performance microprocessor physical design . He is involved in the technology, design porting, physical design, optimization, circuit methodology, signal integrity, timing and CAD tools for several projects. He received his B.Sc degree in physics in1984, and his M.Sc. degree in Electronics in 1987, both from the Aristoteles University Thessaloniki Greece. He received his Ph.D degree in Electrical Engineering in 1994 from the Technical University of Berlin, Germany. From 1991 to 1995 he was the leader of the high performance bipolar ICs design team at the R&D Center of SGS Thomson in England and in Catania, Italy. He was involved in the design of several ICs for telecommunications, in device modeling and process optimization. He holds five patents and has several IEEE publications. He served as a member of the ISSCC Digital Program Committee from 2002-2007 and as Guest Editor for the Journal of Solid State Circuits.

“Achieving highly integrated, re-configurable RF front-ends in deep sub-micron CMOS with an example of a WCDMA, GSM/GPRS/EDGE receiver front-end without inter-stage SAW filter in 90nm CMOS”

by Naveen K. Yanduru, Texas Instruments Inc.

Abstract: Various RF bands, standards, modulation schemes, duplex mechanisms and signal bandwidths needed for the mobile terminal call for a highly adaptable and reconfigurable RF receiver. The biggest bottleneck in achieving this goal lies with the RF pre-select filter at the antenna, which is band specific and creates a bottleneck in being able to share the hardware.

Solving this multi band programmability is the biggest challenge in achieving a RF Receiver for software defined radio. A few of the possible architectures and their limitations are presented. However, designing a multi mode RF receiver for a given RF band with highly reconfigurable performance is an achievable goal.

A WCDMA/EDGE receiver without inter-stage SAW filter in 90nm digital CMOS is used as an example in illustrating the architecture, circuit and system considerations for such a receiver.

Bio: Naveen Yanduru is currently a Design Manager at Texas Instruments Inc., and a Member Grade Technical Staff. While at Texas Instruments he has led design teams in the design of various RF receivers including GSM/EDGE, WCDMA, TDSCDMA, GPS and multi-mode receivers. He is currently involved in the design of DRP™ chips, which are highly integrated ICs in deep sub-micron CMOS processes for mobile phones.

“Multichip module packaging and its impact on architecture”

by Hubert Harrer, IBM

Abstract: The presentation compares the system packaging and technologies of IBM’s latest system z high end servers.

Starting from the z900, the system design change towards a blade-like architecture will be explained. The latest system generation z9 has achieved a doubling of the multiprocessor performance compared to the z990 system by maximizing its CPU configuration in combination with increasing the speed of the interconnections.

The heart of a processor node consists of a multi chip module (MCM) which contains the double core processor chip, the cache chips and the bus adaptors to the memory and the IO chips.

This MCM technology is the key enabler for the high bandwidths between processor chips and the cache chips. The glass ceramic module has accomplished this challenge within the 102 layers resulting in a total wiring length of 545m. The increase of bandwidth requirements for the packaging will be compared for the last generations. Also the complex board and card technology of the second level packaging will be discussed. The cooling of the system is being done with a modular refrigeration unit (MRU), which cools the processor chips down to 45C. This low temperature ensures highest reliability and reduced leakage current of the chips. An air cooled backup mode at a lower frequency ensures that the system does not go down in case of an MRU fail. The MCM has been designed for a maximum power of 850W during nominal operation and 1200W in case of the air-cooled backup mode.

The presentation will focus on the electrical design methodologies for high end servers like power delivery concepts, signal integrity methodologies and power integrity designs for delivering such high currents.

Bio: Dr. Harrer is a Senior Technical Staff Member (STSM) since 2002 working in the IBM Server and Technology Group. He received his Dipl.-Ing. degree in 1989 and his Ph.D. degree in 1992 from the Technical University of Munich. In 1993 he received a DFG research grant to work at the University of California at Berkeley in the paradigm of Cellular Neural Networks. Since 1994 he has worked for IBM in the Boeblingen Packaging Department. In 1999 he was on international assignment at IBM Poughkeepsie, New York. He was leading the z900 MCM designs and is the technical lead for z-series CEC packaging designs since 2001. This includes the system z990 and system z9 mainframe computers. His technical interests focus on packaging technology, high frequency designs and electrical analysis for first and second level packaging. He has published multiple papers and holds 7 patents in the area of packaging.

“Design Techniques and CMOS Implementation of Low Noise Amplifier (LNA)”

by S. S. Jamuar, Universiti Putra, Malaysia

Abstract: The rapid growth of portable RF communication systems in various standards has led to the demand for one chip to cover several standards such as WCDMA, WLAN, GSM etc. This leads to the stringent requirements for the RF front-end to cover a large range of different carrier frequencies for all standards. A receiver system consists of the following circuits: a low noise amplifier, mixer, voltage-controlled oscillator (VCO), intermediate frequency (IF) amplifier and filters. The low noise amplifier (LNA) is typically the first active stage for the RF front-end. Its main function is to amplify low signals without adding noise, thus preserving the signal-to-noise ratio (SNR) of the system at low power consumption. Many tradeoffs are involved in designing the LNA such as noise figure (NF), linearity, gain, impedance matching and power dissipation. Therefore, proper LNA design considerations and techniques are crucial in today’s communications technology.

This lecture places an emphasis on improved design techniques for the low noise amplifier (LNA). DC biasing techniques, impedance matching techniques, noise matching and stability analysis will be discussed. Voltage mode design and current mode design techniques will be elaborated. Variable gain low noise amplifier design techniques will also be discussed. All the design techniques and simulations presented in the tutorial will be based on EDA tools.

Bio: S.S. Jamuar received his M. Tech and Ph. D. in Electrical Engineering from Indian Institute of Technology, Kanpur, India in 1970 and 1977 respectively. He worked as Research Assistant, Senior Research Fellow and Senior Research Assistant from 1969 to 1975 at IIT Kanpur. During 1975-76, he was with Hindustan Aeronautics Ltd., Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT Kanpur, where he was involved in the design of various types of Laser Systems. He joined as Lecturer Electrical Engineering Department at Indian Institute of Technology Delhi in 1977, where he became Assistant Professor in 1980. He was attached to Bath College of Further Education, Bath (UK), Aalborg University, Aalborg (Denmark) during 1987 and 2000. He was a Professor in the Department of Electrical Engineering at IIT Delhi from 1991 to 2003. He was Consultant to UNESCO during 1996 in Lagos State University, Lagos (Nigeria). He was with University Putra Malaysia during 1996-97 in the Faculty of Engineering. Presently he is Professor in the Electrical and Electronic Engineering Department in the Faculty of Engineering, University Putra Malaysia (Malaysia) since 2001. He has been teaching and conducting research in the areas of Electronic Circuit Design, Instrumentation and Communication Systems. He has about 40 papers in the International Journals and has attended several International Conferences and presented papers. He recently received Taiwan Patent on Simulation Circuit Layout Design for Low Voltage, Low Power and High Performance Type II Current Conveyor. He is recipient of Meghnad Saha Memorial Award 1976 from IETE, . Distinguished Alumni Award from BIT Sindri in 1999, Best paper award in IETE journal of Education 2004 from IETE. He is senior member of IEEE and Fellow of Institution of Electronics and Telecommunications Engineering (India). He is on the Editorial Board of Wireless Personnel Communication Journal. He is presently the Chapter Chair for IEEE CAS Chapter in Malaysia. He is one of DLP speakers for the term 2008-2009 for the IEEE Circuits and System Society.