“The Knowledge Sharing Environment”

by Dr. Gene Meieran, Intel

Presentation available in pdf

Bio: Gene Meieran received his BS degree from Purdue University, in 1959, and his ScD degrees from MIT in 1963, in the field of Material Science.

He joined Fairchild Semiconductor R&D in Palo Alto, CA in 1963, responsible for the materials analysis laboratories. He specialized in the characterization and analysis of semiconductor device materials.

He joined Intel in 1973 as Manager of Package Development. In 1977, he joined the Quality and Reliability Staff, with responsibility for Intel materials technology, the Analysis Laboratory, and for key elements of the wafer fab. In 1985, he was appointed as Intel Fellow, the second in the company’s history and a Intel Sr. Fellow in 2003. He has been working on developing advanced manufacturing strategy development in Intel’s Technology Manufacturing Engineering group.

He has published about 50 papers in the fields of SPC, materials analysis, process and product reliability, and manufacturing technology development and has been awarded three international awards based on technical talks. Gene founded the Electronic Materials Symposium which since 1973, sponsors an annual meeting to discuss materials and processing technology for the semiconductor industry. He is the Chair for the Ross Tucker Memorial Awards Committee, which for the past 29 years has donated cash awards to San Francisco Bay-area university graduate students.

Gene has been on the Scientific and Education Advisory Board for Lawrence Berkeley Labs, the Advisory Boards for the Department of Electrical Engineering/Computer Science at UC Berkeley, and is currently on the Board of Advisors for the Materials Science Department at Purdue University and the Board of Visitors at the University of New Mexico, and on the Advisory Board for the Ford Design Institute. He was appointed as Director for Research for the MIT Leaders For Manufacturing Program in 1993, a position he held until 2001. He has served on numerous government and industry panels dealing with manufacturing technology and policy issues, such as the Society of Manufacturing Engineers (SME) Education Foundation and the SRC Factory Systems Board. For three years, he was the American judge at the European Union Science Fair, and has been the Intel judge for the Intel International Science and Engineering Fair for 10 years.

In 1987, Purdue University elected him as Distinguished Engineering Alumni, in 1998 Dr. Meieran was elected to the National Academy of Engineering and in 2000 was named as Purdue University All American Band Alum of the Year.

Gene is a zealous collector of mineral specimens from around the world, and has played the flute in various symphonic bands..

“Applying equation based synthesis to produce optimal pipeline A/D converters”

by Navraj Nandra, Barcelona Design

Presentation available in pdf

Bio: Navraj Nandra joined Barcelona Design in June 2001 as Director of Applications from Austria Mikro Systeme International, where he was U.S. Design Center Manager supporting ASIC and COT designs in high voltage CMOS, SiGe and BiCMOS technologies.

Mr. Nandra has worked in the semiconductor industry since the mid 80’s as an analog IC designer for Philips Semiconductors, EM-Marin (Neuchatel, Switzerland) and Thorn EMI Central Research Labs (UK). He has authored papers in A/D converter design and RFID design. In 1996 he was awarded the best poster for “A Contact-less Read/Write Transponder using Low Power EEPROM technology” at ESSCIRC in Neuchatel.

Mr. Nandra holds a Master of Science degree in microelectronic systems design from Brunel University and a postgraduate diploma in process technology from Middlesex Polytechnic, both in the UK.

“Mixed Signal Verification in Verilog-AMS”

by Jonathan David, Scintera Networks

Presentation available in pdf

Abstract: Differential or Current-Mode Logic (CML) circuits are used in very high-speed applications where standard CMOS gates will not switch fast enough. Due to the size of this market, standard logic design and simulation tools have not been adapted to address this design niche, forcing designers to develop their own tools, or use custom (ie Analog) design tools and simulators. Using Analog simulator for this design space is very time-consuming, limiting the design size that can be worked on in a given timeframe, and usually preventing sufficient verification to be be completed prior to tapeout. Mixed signal simulators using Verilog-AMS netlists are able to address this design space, but examples are not widely available.

In this tutorial presentation Applications of CML logic are introduced, focusing on the Clock Divider for PLL’s operating above 1-2GHz common in communication circuits. An overview of CML circuits and their operation is provided. Starting with a Verilog-A model of a basic gate, the development of a mixed signal model, and the required connect elements and rules are explained, and applied to the simulation of the clock divider. The presentation will close with the application of this circuit to the PLL and the resulting simulation performance improvements.

Bio: Jonathan David leads the Mixed Signal Design Verification team at Scintera Networks, http://www.scintera.com. Prior to joining Scintera, he worked with Cadence Design Systems, assisting customers with the adoption and use of Analog and Mixed Signal simulation tools, and with development of Analog Behavioral Models in the Verilog-A and Verilog-AMS languages.

An active IEEE volunteer, and early adopter, he created the first website for the Santa Clara Valley Section, was instrumental in the founding of both the Solid-State Circuits and Circuits and Systems chapters in the Section, and recently as the chair of the SCV-PACE group, created the first IEEE officer blog in the section at http://ieee-jbdavid.blogspot.com.

“Signal Integrity: Design, Test and Tolerance”

by Dr. Xiaoliang Bai, Magma Design Automation

Abstract: With emergence of nanometer technology, signal integrity is becoming a major challenge to IC industry. With reduced noise margin and increased process variation, circuits become vulnerable to environmental interference and manufacturing defects. In modern designs like SoCs, there are millions of noise-prone nodes need to be analyzed, verified and tested. In this talk, we will briefly present following two topics:

1) Chip may fail to function due to design vulnerabilities, process variation or radiation effects. While it’s expensive and difficult to achieve 100% accuracy in predicting compound noise effects, it is possible to efficiently analyze the aggregated noise impact on the overall robustness, identify the most vulnerable region of a design and subsequently guide repairing/optimization techniques.

2) Noise effects are sensitive to operational parameters such as power supply voltage, frequency and temperature, demanding at-speed testing for AC failures. Software-Based Self-Test (SBST) methodology, as an embedded test and validation solution, combines advantages of structural test and functional test. Not only can it test the circuit in a natural operational environment, it also provides an opportunity of cost-effective self-test and self-repair for SoC designs.

Bio: Dr. Xiaoliang Bai received his Ph.D. degree in 2003 from the department of Electrical and Computer Engineering, University of California, San Diego. Currently, he is a member of technical staff at Magma Design Automation, Inc. He has filed three U.S. Patent applications based on his research. His research interests include signal integrity analysis, design for test, timing analysis and circuit optimization.

“Physical CAD Changes to Incorporate Design for Lithography and Manufacturability”

by Dr. Lou Scheffer, Cadence Design Systems

Presentation available in pdf

Bio: Dr. Lou Scheffer received his BS, MS from Caltech in 1974 and 1975 respectively; and his PhD from Stanford in 1983. Dr. Scheffer started as a chip designer – he then got into CAD and worked for Valid for 10 years. His main research interests are placement, routing, floorplanning and DFM in particular the effects of modern processes and the need for statistical timing. Other interests are SETI and radio astronomy. He has been with Cadence since 1991 and is a Cadence Fellow. He has also been an Associate Editor for IEEE Transactions on CAD.

“Parachuting to a Soft Landing in the Silicon Valley Job Hunt”

by Richard N. Bolles

Abstract: At the top of the ladder, we learn that corporate leaders often get a “golden parachute” to enable them to move to another position with little financial hardship. The rest of us have to make other plans, or find ourselves making these plans when we find ourselves out of work.

Income and job satisfaction are the major reasons engineers take the jobs they do. The “job hunt” is a process of finding a match between the employer’s need and the employee’s capabilities or skills. A Great match allows the employer to make more profit, and reward the employee with a larger income. However, even in today’s Internet world, the process of finding a good match between employer and employee still seems to be sub-optimal.

Following the cancellation of the U.S. Apollo program, IEEE members experienced an economic dislocation that was quite unexpected at the time, considering the value the country had put on the engineering profession, and the electronics industry up to that point in time. On the frontline of helping these highly trained individuals find new work, Dick Bolles published a guide to the job hunting process in 1970, called “What Color is Your Parachute?”, which offered a better approach to the job hunt than “find the ad, mail a resume, wait and hope.” The book has since become known as “the Job Hunter’s Bible” [see www.jobhuntersbible.com] and is now updated annually.

While the internet speeds up the process by which one can “find a posting, email a resume, wait for an interview”, many find it just increases the rate of rejection. Since the principles of a better matching process still hold true, the IEEE Santa Clara Valley PACE has arranged for a discussion of the job search process by the author to assist the members in the section who are facing a job transition now, or may face one in the near future.

Bio: Richard Nelson Bolles, known the world over as the author of the best-selling job-hunting book in history, “What Color Is Your Parachute?,” is acknowledged as “America’s top career expert” by Modern Maturity Magazine, “the one responsible for the renaissance of the career counseling profession in the United States over the past decade” by Money Magazine, and “the most widely read and influential leader in the whole career planning field” by the U.S. Law Placement Assn. Dick is listed in “Who’s Who In America,” and “Who’s Who In the World” and has been featured in countless magazines (including Reader’s Digest, Fortune, Money Magazine and Business Week), newspapers, radio, and TV (CNN, Ted Koppel, ABC’s Nightline, Diane Sawyer, CBS News and many others).

Dick Bolles was born in Milwaukeee, Wisconsin, grew up in Teaneck, N.J., where he attended and graduated from high school. He served in the U.S. Navy and worked as a messenger on Wall Street before attending college. The author’s academic background is in engineering, physics, and Biblical studies. Having majored in chemical engineering during his two years at the Massachusetts Institute of Technology, Bolles transferred to Harvard University and earned a bachelor’s degree in physics (cum laude). He also holds a master’s degree in New Testament studies from the General (Episcopal) Theological Seminary in New York City, is a member of MENSA and the recipient of two honorary doctorates.

Bolles lives in the San Francisco Bay Area, and has five grown children: Stephen, Mark, Gary, Sharon, and Serena (his step-daughter). Dick’s grandfather was a U.S. congressman, and his father an editor for the Associated Press. His brother was the famous investigative reporter Don Bolles, who was assassinated in Phoenix, Ariz., in 1976. Dick’s sister, Ann Johnson, lives in Mt. Holly, N.J.