“Clean/Green Technologies”

by Dr. William Kao

Presentation available in pdf

Abstract: Dr. Kao will give an overview of the latest trends and developments on clean technology. While his focus in last year’s CAS presentation was on Renewable Energy (energy source), this year’s talk will be on:

1. Energy transmission and distribution aka smart grid;
2. Energy Storage technologies, lithium ion batteries;
3. Green Building : Leadership in Energy and Environmental Design (LEED), LED lighting and biomimicry;
4. Green Transportation: electrical vehicles, and PHEVs.

Bio: Dr. William Kao received his BSEE, MSEE and PhD from the University of Illinois Urbana-Champaign. He has worked in the Semiconductor and Electronic Design Automation industries for 30 years holding senior and executive (Director, VP) engineering management positions at Texas Instruments, Xerox Corporation, and Cadence Design Systems. Dr. Kao has authored more than 40 technical papers and holds several software and IC patents. He was an Adjunct Professor at UCLA Electrical Engineering Department where he taught courses in computer aided circuit design. Dr. Kao is a Senior Member of IEEE, and was one of the founding members of IEEE-CAS Silicon Valley Chapter, where he was Chapter Chair in 2006. Dr. Kao currently teaches Renewable Energy and Clean Technology courses at UC Santa Cruz Silicon Valley Extension, and at the Silicon Valley Technical Institute in San Jose. He is also on the Technical Advisory Board for Sigma Quest on the topics of Energy and Environment, and Quality Control, and is a consultant for several Clean Tech companies. Dr. Kao is currently President and Founder of CARES (Chinese American Renewable Energy Society) , now The Clean Technology Group of the Chinese Institute of Engineers (CIE) USA-SF, where he is also a Board Member.

“Future Directions in Mixed-Signal IC Design”

by Prof. Boris Murmann, Stanford

Presentation available in pdf

Abstract: This talk provides a summary of Prof. Murmann’s research in the area of mixed-signal integrated circuit design. Focus is placed on examples that either look at “old” problems with “new” eyes, or tackle “new” problems by leveraging state-of-the art technology. Specific topics include digitally assisted data converters, interface circuits for MEMS and bio-medical applications, as well as large-area organic thin-film electronics.

Bio: Boris Murmann is an Assistant Professor in the Department of Electrical Engineering, Stanford, CA. He received the Ph.D. degree in electrical engineering from the University of California at Berkeley in 2003. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In 2008, Dr. Murmann was a co-recipient of the the Best Student Paper Award at the VLSI Circuit Symposium and the recipient of the Best Invited Paper Award at the Custom Integrated Circuits Conference (CICC). In 2009, he received Agilent Early Career Professor Award.

“Energy-Efficient Design of Digital Circuits”

by Prof. Vojin Oklobdzija, University of Texas, Dallas

Abstract: Techniques for designing and optimizing digital circuits have for a long time been driven by performance. Power is now the limiting factor to performance. Logical Effort technique helps to determine transistor sizes for speed as an objective function. However, it neglects energy issues and fails to provide a guideline when designing with power budget. Other techniques have been presented which opportunistically improve power, or degrade performance to reduce power. These approaches do not directly address the true concern of digital designers, which is obtaining the minimal energy for a given performance. How to make energy-delay trade-offs for the optimal design point is neither well understood nor well defined. Design space is bound by maximally achievable speed and minimal achievable power. This presentation addresses the factors impacting optimization of digital circuits, and a framework for the optimal sizing, comparison, and analysis of energy-efficient designs.

Bio: Vojin G. Oklobdzija, is an IEEE Fellow, Distinguished Lecturer of the IEEE Solid-State Circuits Society, Vice-President of IEEE CAS and Member of the IEEE CAS Board of Governors. He received Dipl. Ing. degree from the School of Electrical Engineering, University of Belgrade in 1971, and Ph.D. from UCLA in 1982. During his PhD he worked at Xerox Corp. Microelectronic division and was involved in early workstation development Xerox Alto.

From 1982 to 1991 he was at the IBM Thomas J. Watson Research Center, where he made contributions to the development of RISC processors, super-scalar and supercomputer design. In the course of this work, he obtained several patents, the most notable one on register renaming, which enabled a new generation of modern computers.

From 1988 to 1990 he was IBM visiting faculty member at the University of California at Berkeley, from 1991-2006 professor of computer engineering at the University of California Davis, 2006-2007 Chair Professor at Sydney University and currently Professor at the University of Texas in Dallas. Prof. Oklobdzija actively served as a consultant to Sun Microsystems, Bell Laboratories, Texas Instruments, Hitachi, Fujitsu, SONY, Intel, Samsung and Siemens Corp. (where he was a principal architect for the Infineon TriCore processor). Dr. Oklobdzija has provided litigation consulting and expert witness services to major legal firms in USA and abroad including: Townsend and Townsend, Arent Fox, Kellogg Huber, Dechert LLP, DLA Piper US LLP and BLB&G. He holds 15 U.S., 6 European, 6 Japanese, 6 international and 2 other patents pending.

Prof. Oklobdzija is serving on the Editorial Board of IEEE MICRO and publishing board of Taylor-Francis, IEEE Fellow Committee, and numerous other IEEE committees. He served as the Associate Editor of IEEE Transaction on Computers from 2000-2006, IEEE Transactions on VLSI from 1995-2003, IEEE Transaction on Circuits and Systems II and Journal of VLSI Signal Processing, the ISSCC program committee from 1996 to 2003 and again in 2007, First Asian ASSCC, International Symposium on Low-Power Design, Computer Arithmetic, ICCD, PATMOS and numerous other conference committees. Currently he is General Chair for the International Symposium on Low-Power Design, ISLPED 2010 and 20th Int’l Symposium on Computer Arithmetic, ARITH-20. He was a General Chair of the ARITH-13 (1997), DCAS-2008, IASTED Conference on Circuits, Signals and Systems (2006), Technical Program Chair for ISLPED 2008 and Track Chair for ICCD 2008. Prof. Oklobdzija has published 170 papers, 6 books and dozen of book chapters in the areas of circuits and technology, computer arithmetic and computer architecture. His book “Computer Engineering” won Outstanding Academic Title award, out of 22,000 titles considered and is currently in second edition. He has given over 200 invited talks and short courses in the USA, Europe, Latin America, Australia, China and Japan.

As Emeritus Professor of the University of California he directs ACSEL laboratory which is involved in digital circuits optimization for low-power and ultra low-power, high-performance system design and sensor nodes. (for further information please see: http://www.acsel-lab.com).

“The Smart Grid: A Convergence of IT, Communications and Power and Energy Technologies”

by Claudio Lima, Sonoma Innovation

Abstract: The Smart Grid is emerging as a convergence of Information Technology (IT), Communications and Control technology with Power and Energy System Engineering. Today’s electricity grid is inefficient, where 8% of its output is lost along its transmission line and an over dimensioned generation capacity of 20% exists to meet peak demand that it’s used only 5% of the time. Also, the lack of real-time information and control of the critical processes and assets creates the domino-effect that is responsible for major blackouts and failures in the system, which accounts for billions of dollars in losses. The next generation electricity grid is a “smarter” grid, where pervasive and intelligent control devices and bi-directional and real-time communications systems are overlaid on existing electricity infrastructure to provide new energy services to the end customers and make the grid more secure, reliable and efficient.

The Smart Grid is also being considered as the next big “Internet of Things” as billions of pervasive and intelligent devices will be deployed and controlled at the customer premises and throughout the transmission and distribution networks. It’s estimated that each house will have at least six new intelligent devices, each with it’s own IP address. This “data explosion” will unleash new opportunities in IT, Software, Communications and Semiconductors development, creating the next big wave of innovation for start-ups, VCs, and entrepreneurs in Silicon Valley.

The attendees will gain a broad perspective of the key Smart Grid concepts; the drivers, benefits and key challenges for deploying Smart Grid systems today. The talk introduces the Smart Grid building blocks, identifies the key elements of an End-to-End Smart Grid system, introduces the NIST Smart Grid standards roadmap and the Smart Grid Innovation Zones.

Bio: Claudio Lima is the Managing Director of Sonoma Innovation, a Silicon Valley-based Smart Grid Consulting Firm, specialized in SmartGrid Communications Strategy, Next GenerationSmart Grid Architectures and Advanced Smart Grid Technologies. He’s a Member of The Smart Grid Council (SGC) and The IEEE Smart Grid (SGSC) Steering Committees, Vice-Chair of the IEEE Smart Grid Architecture work group and serves as a Member of the NIST Cybersecurity Smart Grid Architecture and the IEEE P2030 Smart Grid Standards Committee.

He’s actively involved developing the NIST Smart Grid Interoperability (SGIP) Standards, defining the role of IP in Smart Grid and the developing an End-to-End Smart Grid Communications Architecture Framework. Prior to joining Sonoma, Dr Lima headed several teams and strategic initiatives for Sprint-Nextel at the Sprint Advanced Technologies/CTO organization in Silicon Valley, including Sprint’s Next Generation Networks, Emerging Services, and Digital Media Innovation (DMI)/Venture-R&D, responsible for new technologies and business development for Sprint-Nextel’s. He has 22 years of experience Leading Advanced Telecommunications Systems, Architectures and Next Generation Communications Services Development. He holds a Ph.D. in Electronic Engineering from the University of Kent, Canterbury-England and an Executive MBA from Dom Cabral Foundation (FDC).

“Emerging Frequency Synthesis Techniques for the Current and Future Advanced CMOS Technologies”

2-day short courses by Dr. Paul P. Sotiriadis, Liming Xiu and Prof. R. Bogdan Staszewski

August 14 – 15, 2010

Program available in pdf

Abstract: The task of clock-generation becomes increasingly difficult as we move into the nanometer-scale CMOS technologies. The single most dominant reason behind these difficultness is that these advanced CMOS technologies are designed mainly to handle digital signals. They are not analog friendly. The traditional electronic circuitry is naturally destined to handle its internal signal’s voltage/current level, not the timing. Within the electronic circuitry, the timing information is only indirectly implied by its signal’s crossing of certain voltage/current threshold levels. Therefore, traditionally, the task of clock-generation (where timing is the primary design variable) is mainly dealt with by analog-intensive circuitry since the traditional analog circuitry can handle much more voltage/current levels than its digital counterpart can. When chip design moves into the regime of advanced CMOS nodes where two-level digital signal is the main design entity, innovative timing approaches have to be created to meet this new challenge: using best of the digital plus minimum of analog.

On another front, modern designs suffer from excessive on-chip component-count, and are extremely complex in terms of functionality. To support this large number of sequential elements and sophisticated timing requirement, the on-chip clock-generation-circuitry has to be efficient both in producing frequencies and in consuming resources (area, power, etc). The clock circuitry designer is constantly under tremendous pressure of creating better designs at lower cost.

The task of clock-generation is at the central focus point of modern VLSI design. To find better solutions for future, researchers and engineers around the world are relentlessly exploring various methods. Among them, two approaches have emerged with great potential: Time-Average-Frequency based Flying-Adder frequency synthesis technology and All Digital PLL (ADPLL, see book in SC#3). Both of them are born from the battleground of designing real commercial products. In this short course, these two emerging technologies will be introduced in great detail.

Short Course #1: Emerging Frequency Synthesis Techniques for the Current and Future Advanced CMOS Technologies by Dr. Paul P. Sotiriadis, Sotekco Electronics LLC

Short Course #2: Time-Average-Frequency Flying-Adder Frequency Synthesis Architecture and Digital-to-Frequency Converter by Liming Xiu, Novatek

Short Course #3: All-Digital Frequency Synthesizer in Deep-Submicron CMOS by Prof. R. Bogdan Staszewski, Delft University of Technology

Bios:

Paul P. Sotiriadis (S’99, M’02) received the Ph.D. degree in EECS from MIT in 2002 under the supervision of Prof. Anantha Chandrakasan, and the MSEE from Stanford University in 1996. In 2002 he joined Johns Hopkins University as assistant professor of ECE. In 2007 he joined Apex/Eclipse INC as the Chief Technology Officer and shortly after he started Sotekco Electronics LLC, an electronics research company in Maryland, USA. He is interested in the design, optimization, and mathematical modeling of analog, mixed-signal RF and microwave EEE SCV-CAS August’10 2-Day Course “Emerging Frequency Synthesis technique for current and future Advanced CMOS technologies” circuits with special emphasis in advanced frequency synthesis and deep-sub-micron technologies. He has led several projects in these fields funded by US organizations and has collaborations with industry and National labs. He has authored and co-authored more than seventy technical papers in IEEE journals and conferences, most of them as the leading or single author. He has served as an associate editor of the IEEE Transactions on Circuits and Systems II and is a member of several technical and conference committees.

Liming Xiu is the inventor of Flying-Adder frequency synthesis architecture which has been used in many commercial products with revenue of over 500-millions US dollar. During his professional career, he has published many journal papers on Flying-Adder related topics. He holds sixteen granted and pending patents. He is also an industry expert on VLSI SoC integration with battle-proven integration experience on several very large chips in advanced CMOS nodes. In this area, he has one book published: “VLSI Circuit Design Methodology Demystified”. Both TI CEO (Richard Templeton) and CTO (Hans Stork) have written forewords for this book. Liming Xiu has the experience and skill of a practical engineer. Moreover, he also possesses the vision and capability of a frontline researcher with energetic passion for innovation. His career goal is to spread this groundbreaking Flying-Adder/Time-Average-Frequency/Digital-to-Frequency-Converter technology within the industry, to serve the mission of creating cheaper, better, more efficient electronic products. He is an IEEE CAS VP for Region 1-7, a Chief Clock Architect at Novatek (novatek.com.tw), was a Senior Member of Technical Staff (SMTS) at Texas Instruments Inc. during 1995-2009.

R. Bogdan Staszewski received BSEE (summa cum laude), MSEE and PhD from University of Texas at Dallas in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel in Richardson, TX, USA. He joined Texas Instruments in Dallas, TX, USA in 1995. In 1999 he co-started a Digital RF Processor (DRPTM) group with a mission to invent new digitally-intensive approaches to traditional RF functions. Dr. Staszewski was appointed a CTO of the DRP group between 2007 and 2009. Since July 2009 he is Associate Professor at Delft University of Technology in the Netherlands. He has co-authored one book, two book chapters, 110 journal and conference publications, and holds 60 issued 40 pending US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers. He is an IEEE Fellow.

“Micropower Low-Voltage Digital Class D Amplifier”

by Prof. Bah-Hwee Gwee, Nanyang Technological University

Presentation available in pdf

Abstract: As portable digital audio devices (including hearing aids) continue to proliferate and more functions continue to be augmented in these devices, the question of battery lifespan is often a critical design parameter. In these advanced digital audio devices, the audio power amplifier is typically a digital Class D amplifier (switching amplifier) instead of the more classical linear audio amplifier. In this talk, we will discuss the design of digital Class D amplifiers, with emphasis on the computation of the modulation for low power, appropriate for portable digital devices. The computation of the modulation includes Pulse Width Modulation, Pulse Density Modulation, and the Hybrid scheme. The non-linearities that affect the fidelity of these amplifiers will also be discussed.

Bio: Dr. Bah-Hwee Gwee received his B.Eng. degree from University of Aberdeen, UK, in 1990. He received his M.Eng. and Ph.D. degrees from Nanyang Technological University (NTU), Singapore in 1992 and 1998 respectively. He is currently an associate professor in School of EEE, NTU. He has been working on a number of funded research projects amounting to SGD $5.6m (~ US$4m). He is the PI/co-PI of projects including the DARPA project from USA, the AUNP project from EU, Panasonic Semiconductors (Singapore) research project, Linkoping University (Sweden)-NTU research collaboration project, Singapore Defence Science Project and Academic Research Funded Projects.

He was the Chairman of IEEE CAS Singapore Chapter in 2005 and 2006. He is the committee member of IEEE CASS VLSI Systems TC, DSP TC, BioCAS TC and Life Science TC. He was the organizing committee of IEEE Bio-CAS 2004, IEEE APCCAS 2006 and the Programme Chair of ISIC 2007 and ISIC 2011. He is a senior member of IEEE, Associate Editors of IEEE Transactions on Circuits and Systems II: Brief Express and Journal of Circuits, Systems and Signal Processing, and the IEEE CASS Distinguished Lecturer. His research interests include asynchronous circuit design, ultra-low power sub-threshold design, Class-D amplifier design and digital hearing aid design. He has several circuit design patents granted and co-founded a start-up Company in 2005.

“Ultra Low Voltage VLSI Design for Minimum Energy Computing”

by Prof. Massimo Alioto, University of Siena

Abstract: In the last years, subthreshold CMOS logic circuits have become very popular in ultra low power applications, which typically constrain the power budget to a few tens of µWs and the supply voltage to a few hundreds of mV. Designing at such low power and low voltage is challenging and requires a deep understanding of the power delay tradeoff, as well as of the impact of design variables and variability sources on the circuit robustness.

In this talk, a survey of fresh ideas and recent techniques to design and implement subthreshold CMOS logic circuits is presented. Novel circuit models of subthreshold CMOS logic in nanometer technologies are presented to understand its basic properties. The models are then used to derive design criteria to meet assigned constraints in the power delay design space, as well as to counteract with the issues that arise in nanometer technologies (process/voltage/temperature variations, leakage power, robustness…). Limitations under nanometer technologies are addressed in the scaling perspective. Design techniques are discussed at the physical, transistor, gate and system level of abstraction. Detailed guidelines on how to build ultra low power standard cell libraries are derived, and examples are provided. A detailed comparison of design flows targeting standard and subthreshold CMOS logic is also presented to understand how to specifically build design flows for ultra low power. Successful designs and state of the art chips are presented to gain a clear understanding of the state of the art, and which direction the research is moving to.

Bio: Massimo Alioto (M’01-SM’07) was born in Brescia, Italy, in 1972. He received the laurea degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively. In 2002, he joined the Dipartimento di Ingegneria dell’Informazione (DII) of the University of Siena as a Research Associate and in the same year as an Assistant Professor. In 2005 he was appointed Associate Professor of Electronics, and was engaged in the same faculty in 2006. In the summer of 2007, he was a Visiting Professor at EPFL – Lausanne (Switzerland). In 2009-2010, he is Visiting Professor at BWRC – UCBerkeley, investigating on ultra-low power circuits and wireless sensor nodes.

Since 2001 he has been teaching undergraduate and graduate courses on advanced VLSI digital design, microelectronics and basic electronics. He has authored or coauthored more than 140 publications on journals (50+, mostly IEEE Transactions) and conference proceedings. Two of them are among the 25 most downloaded TVLSI papers in 2007 (respectively 10th and 13th). He is coauthor of the book Model and Design of Bipolar and MOS Current Mode Logic: CML, ECL and SCL Digital Circuits (Springer, 2005). His primary research interests include the modeling and the optimized design of CMOS high performance, low power and ultra low power digital circuits, arithmetic and cryptographic circuits, interconnect modeling, design/modeling for variabilitytolerant and low leakage VLSI circuits, circuit techniques for emerging technologies. He is the director of the Electronics Lab at University of Siena (site of Arezzo).

Prof. Alioto is an IEEE Senior Member and a member of the HiPEAC Network of Excellence. He is the Chair Elect of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society, for which he is also Distinguished Lecturer. He is regularly invited to give talks and tutorials to academic institutions, conferences and companies throughout the world. He has served as a member of various conference technical program committees (ISCAS, PATMOS, ICM, ICCD, CSIE) and Track Chair (ICECS, ISCAS, ICM, ICCD). He serves as Associate Editor of the IEEE Transactions on VLSI Systems, as well as of the Microelectronics Journal, Integration, The VLSI journal and the Journal of Circuits, Systems, and Computers. He is Guest Editor of the Special Issue “Advances in oscillator analysis and design” of the Journal of Circuits, Systems, and Computers (2009), and Technical Program Chair for the ICM 2010 conference.

“Silicon Photonics: Opportunities & Challenges”

by Dr. Haisheng Rong, Senior Scientist, Intel Labs

Abstract: Silicon photonics technology offers promising low-cost optoelectronic solutions for many applications ranging from optical communications to emerging areas such as optical sensing and analysis. In recent years, rapid progress has been made in developing various silicon-based photonics building blocks. This talk will give an overview of research being done at Intel in the area of silicon photonics, highlighting the recent results and applications, and discussing the opportunities and challenges of optoelectronics integration.

Bio: Dr. Haisheng Rong is a senior scientist in the Photonics Technology Group of Intel Labs. He has worked in many areas of optical and laser technologies during his career including optical information processing, high-resolution laser spectroscopy, large-scale laser interferometer, and optical communications and interconnects. He has published numerous scientific papers including two in Nature and given over 20 invited and keynote presentations at major international conferences and meetings including SPIE conferences, CLEO, OFC, and LEOS meetings. He has won various Intel awards including the highest Intel Achievement Award. In November 2005, he was recognized by Scientific American as one of the top 50 research leaders in science and technology for his work on development of silicon Raman lasers. He received his Ph.D. degree from the University of Heidelberg, Germany. Prior to joining Intel Corporation, he also held engineering position at New Focus, and research positions at MIT and Caltech. He is a Senior Member of IEEE.

“Intellectual Property (IP) Primer for Entrepreneurs and Early-Stage Companies”

by Jordan Becker, Perkins Coie LLP

Joint meeting with SCV-CS, SCV-EDS, SCV-ES & SCV-SSCS chapters

Presentation available in pdf

Abstract: Intellectual Property (IP) Primer for Entrepreneurs and Early-Stage Companies The presentation provides an overview of the various different forms of IP, including their overlap and differences, with most of the remainder of the presentation focusing on patents. The presentation discusses what is a patent, why patents are beneficial or necessary, the different types of patents and patent applications, the legal requirements for obtaining a patent, factors in deciding whether to apply for a patent, when to apply, a summary of the application process, and foreign/international patent protection.

There is normally some time for Q&A, and with some advance notice I can modify or tailor the presentation to address any specific IP-related issues that may be of interest to you and/or the group.

Bio: Jordan Becker is a partner in the firm’s Intellectual Property (IP) group who leverages his engineering background in securing IP protection for technology-oriented clients. His law practice focuses on patent, copyright and trademark prosecution/procurement, counseling clients and developing IP protection strategies and programs for clients, providing non-infringement/invalidity opinions and freedom-to-operate opinions, performing IP due diligence for corporate transactions, pre-enforcement investigations and analyses, and providing legal and technical analysis in support of IP litigation. His clients range from small start-up companies to large, public corporations, both domestic and international.

With a degree in electrical engineering and prior experience as a design engineer, he has extensive experience in securing patents and other IP rights for clients in a wide variety of technology areas, including: medical devices (e.g., medical imaging systems, surgical tools and support equipment), software (e.g., operating systems, mobile computing/communication, online “virtual worlds” and gaming, e-commerce, multimedia processing, search, knowledge management, speech recognition, application delivery/streaming, digital rights management (DRM)), computer architecture, display devices, network storage (SAN/NAS), telecommunications, semiconductor device design/fabrication, and satellite-aided navigation, surveying and construction.

“Tutorial on Status of knowledge on non-binary LDPC decoders”

by Prof. David Declercq, ENSEA in Cergy-Pontoise

Joint Tutorial with SCV-SSCS, SCV-SPS, SCV-CAS & SCV-ComSoc chapters

Abstract: In this tutorial, the iterative decoding techniques for non-binary LDPC codes will be presented, both from the theoretical aspects of Belief Propagation and its analysis, and from more practical aspects of efficient implementation. In a first part, the main difference between iterative BP decoding of binary and non-binary LDPC codes will be highlighted. Then, in a second part, the solutions proposed in the literature to reduce the complexity of non-binary decoders, both for memory storage and computational burden reduction, will be presented. Some directions of research and development about non-binary decoders will be discussed. Finally, the outstanding advantages of generalized non-binary decoders on clustered graphical models of several error correcting codes will be presented.

Bio: David Declercq was born in June 1971. He graduated his PhD in Statistical Signal Processing 1998. He worked on a new Gaussianity test based on Hermite polynomials properties, and the characterization and the blind identification of non-linear time series. After his PhD, he oriented his researchs towards digital communications, and especially coding theory and iterative decoder design. He started to work on LDPC codes in 1999, both from the code and decoder design aspects.

Since 2003, he made a major effort in studying and developping LDPC codes and decoders in high order Galois fields GF(q), with q>>2. A large part of his research projects are related to non binary LDPC codes. He mainly investigated two directions: (i) the design of GF(q) LDPC codes for short and moderate lengths, and (ii) the simplification of the iterative decoders for GF(q) LDPC codes with complexity/performance tradeoff constraints.

David Declercq published more than 20 papers in major journals (IEEE-Trans. Commun., IEEE-Trans. Inf. Theo., Commun. Letters, EURASIP JWCN), and more than 70 papers in major conferences in ICT. He is currently full professor at the ENSEA in Cergy-Pontoise, France, a graduate school in Electrical Engineering. He is a member of the ETIS laboratory, general secretary of the National GRETSI association, and member of the GdR-ISIS direction team. He is currently the recipient of junior position at the “Institut Universitaire de France”.