“Automated Behavioral Modeling: A Quantum Jump in Mixed-Signal Design Verification Technologies”

by Prof. Richard Shi, University of Washington

Abstract: Verification is becoming the number-one bottleneck in mixed-signal systems-on-chip (SoC) design. This talk introduces a new design and verification methodology based on the automated generation of high-level behavioral models from a SPICE netlist. The new methodology is fully compatible with existing design flows yet offers 100x to 1000x reduction in the SPICE simulation time. Analog assertions can be automated, paralleling the well-accepted digital verification methodology.

Bio: Richard Shi is a Professor in Electrical Engineering at the University of Washington, Seattle, where he is teaching VLSI design. He has supervised over 20 PhD students and post-doctoral fellows in the area of circuit simulation, model compilation, analog layout automation, cirucit optimization, and behavioral modeling. He has served as an Associate Editor for IEEE Transactions on Computer-Aided Design for the past ten years. He received several best paper awards including Donald Pederson Best Paper Award. He advised two EDA startups Apteq (A Verilog-A compiler Company) and Gemini (A Parallel SPICE company): both acquired by Synopsys. He is a co-founder of Orora Design Technologies, Inc., focusing on automating mixed-signal design and verification. He has been elected to an Fellow of IEEE for his contribution on computer-aided design of mixed-signal integrated circuits.

“Mixed-Signal Design Verification, an RF-SOC approach”

by Jesse E. Chen and Jonathan B. David, Qualcomm

Presentation available in pdf

BMAS 2010 conference paper (pdf)

Abstract: With 80% of Industry SOC projects containing 20%+ Mixed-Signal content, and 70% of Industry SOC re-spin issues being AMS in nature, (http://eda360insider.wordpress.com/2010/11/05/70-of-re-spin-issues-are-ams-in-nature-how-mixed-signal-design-can-mess-up-a-perfectly-good-soc/) design verification for SOC’s must include a mixed-signal component, especially if the mixed-signal content includes a Radio. The Qualcomm RF/Analog Verification team will present 2 recently published papers in this arena, 1 describing the modeling methodology used at Qualcomm, the other presenting an example of the methodology as applied to the Mixer circuit in a typical receiver path. Use of this methodology eliminates most of the AMS functional issues, so that most remaining re-spins are for AMS/RF parametric issues only, allowing a production ramp on the second spin, rather than the third or fourth.

Bio: Jesse Chen heads up the RF/Mixed-Signal Verification teams for the RFA department in Qualcomm Santa Clara. A Bay-Area native, Jess has a BA (Physics & Math) from Berkeley, MSEE from SJSU, MSME from Santa Clara, and earned the Engineer, EE from Stanford. When Jess is not working, you will either find him commuting home on his Recumbent Bicycle, leading the Bay Area Trail Stompers on a hike, or working on his ham radios (WB6MCC), when he’s not off visiting his grandkids. Prior to joining Qualcomm, Jess has worked at Lockheed, Cadence, RFMD, RFco, and Berkana Wireless.

Jonathan David is a Mixed Signal Verification Engineer at Qualcomm RFA in Santa Clara. Jonathan earned his BSEE from Oregon State, and his SEE from the University of Maryland, College Park. When schedules permit he bikes to work, volunteers with the IEEE (CAS and GOLD groups) and is an avid reader, especially of Science Fiction. Prior to joining Jess at Qualcomm, Jonathan worked at Westinghouse (Baltimore), Cadence, and Scintera Networks.

“Next Generation Wireless Communication Systems”

by Yoshikazu Miyanaga, Hokkaido University

Presentation available in pdf

Abstract: Currently sophisticated wireless technologies, such as digital broad casting, wireless LAN and wireless PAN, have enabled high-speed data transmission in home and personal networks. The IEEE802.11a based wireless LAN supports the maximum of 54 Mbps at a 20-MHz frequency band by using orthogonal frequency division multiplexing (OFDM).

As the next wireless LAN system, the Enhanced Wireless Consortium (EWC) proposal set a goal to achieve the maximum of 600 Mbps using a multiple-input and multiple-out (MIMO) stream technique with OFDM. The EWC proposal was to be adopted in the IEEE802.11n standard. The standardization of IEEE802.11n was concluded in 2009 autumn. There are four main modifications from the IEEE802.11a standard, i.e., a 40-MHz baseband bandwidth, a 400-ns short guard interval, 5/6 coding rate and a 4×4 MIMO scheme. A new study group of IEEE802.11, i.e., IEEE 802.11ac, has started since the last year and they would like to develop “Over Giga Bit” Wireless Networks. In this topic, a system “over 1G” bps throughput, “over 80MHz” bandwidth and “less than 6GHz” carrier is introduced.

Our past system had the goal to achieve the data rate of 600 Mbps by use of an 80-MHz baseband bandwidth and a 2×2 MIMO scheme several years ago. This system occupies a double bandwidth compared with IEEE 802.11n. If we apply 4×4 MIMO scheme as the next system, we can design a 1.2G bps wireless communication system. This is one of candidates on the Next Generation Wireless Communication Network.

This topic describes the VLSI implementation of our proposed 4×4 MIMO-OFDM (2.6G bps with 160MHz BW) and 8×8 MIMO-OFDM systems. A low-latency and a full-pipelined architecture are employed for all processing blocks to provide the real-time operations on OFDM modulation and MIMO detection. The designed transceiver has been evaluated in the circuit size and power dissipation by using a 90-nm CMOS process. In an FPGA board, the proposed total system has been implemented. For the designed system, the circuit behavior on gate size and power consumption is verified. The communication performance is also evaluated.

Bio: He received the B.S., M.S., and Dr. Eng. degrees from Hokkaido University, Sapporo, Japan, in 1979, 1981, and 1986, respectively. Since 1983 he has been with Hokkaido University. He is now Professor at Division of Information Communication Systems in Graduate School of Information Science and Technology, Hokkaido University. From 1984 to 1985, he was a visiting researcher at Department of Computer Science, University of Illinois, USA.

His research interests are in the areas of speech signal processing, wireless communication signal processing and low-power comsuption VLSI system design. He has published 3 books, over 100 Transaction/Journal papers, and more than 200 International Conference/Symposium/Workshop papers.

Dr. Miyanaga served as an associate editor of IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science from 1996 to 1999, editors of IEICE Transactions on Fundamentals, Special Issues. He is also an associate editor of Journal of Signal Processing, RISP Japan (2005-present).

He was a delegate of IEICE, Engineering Sciences Society Steering Committee, i.e., IEICE ESS Officers from 2004 to 2006. He was a chair of Technical Group on Smart Info-Media System, IEICE (IEICE TG-SIS) during the same period and now a member of the advisory committee, IEICE TG-SIS. He is now vice-President, IEICE Engineering Science (ES) Society. He is fellow member of IEICE.

He is also vice-President, Asia-Pacific Signal and Information Processing Association (APSIPA). The APSIPA is a new association established in Hong Kong since 2008 and it promotes all aspects of research and education on signal processing, information technology, and communications.

He served as a member in the board of directors, IEEE Japan Council as a chair of student activity committee from 2002 to 2004. He was a chair of student activity committee in IEEE Sapporo Section (1998-2006) and is a chair of member development (2007-present).

He was a secretary of IEEE Circuits and Systems Society, Technical Committee on Digital Signal Processing (IEEE CASS DSP TC) (2004-2006) and was its chair (2006-2008). He is a distinguished lecture (DL) of IEEE CAS Society (2010-present) and also a Board of Governor (BoG) of IEEE CAS Society (2011-present). He has been serving as a chair of international steering committee, IEEE ISPACS (2005-2007), and IEEE ISCIT (2006-present). He is also an international steering committee member of IEEE ICME, IEEE/EURASIP NSIP, IEICE SISA et. al. He was an honorary chair and general chair/co-chairs of some international symposiums/workshops, i.e., ISCIT 2005, NSIP 2005, ISCIT 2006, SISB 2007, ISPACS 2008, ISMAC 2009, ISMAC2010, APSIPA ASC 2009, IEICE ITC-CSCC 2011, APSIPA ASC 2011 and IEEE ISCIT 2012.

“CleanTechnology: Recent Trends and Developments”

by Dr. William Kao

Abstract: In this talk Dr. Kao will cover most recent trends in renewable energy (solar, wind), energy storage, smart grid technologies, green transportation (HSR, EV), and Clean/Green Technology Jobs.

Bio: Dr. William Kao received his BSEE, MSEE and PhD from the University of Illinois Urbana-Champaign. He has worked in the Semiconductor and Electronic Design Automation industries for 30 years holding senior and executive engineering management positions at Texas Instruments, Xerox Corporation, and Cadence Design Systems.

Dr. Kao has authored more than 40 technical papers and holds many software and IC patents. He was an Adjunct Professor at UCLA Electrical Engineering Department where he taught courses in computer aided circuit design. Dr. Kao is a Senior Member of IEEE, and was one of the founding members of IEEE-Circuits and Systems – Silicon Valley Chapter, where he was Chapter Chair in 2005 and 2006.

Dr. Kao currently teaches Renewable Energy, Clean Technology and Business Sustainability courses at UC Santa Cruz Silicon Valley Extension, and at the Silicon Valley Technical Institute in San Jose.

He is also a technical advisor and consultant for several local Clean Tech companies.

Dr. Kao was the founder and President of CARES (Chinese American Renewable Energy Society), now The Clean Technology Group of the Chinese Institute of Engineers (CIE) USA-SF, where he is currently a Board Member.

Most recently, Dr. Kao was a Clean Technology consultant for mainland China Government where he taught courses on “Low Carbon Economy” to Chinese government officials; for the Taiwan Ministry of Science and Technology where he was invited to give seminars on Clean Technology, Renewable Energy, and Energy Efficiency at major universities (academia), and government research institutions; and for the Malaysian Government on ‘Emerging Technologies’ for a new Knowledge Based Economy.

“Physical Verification Challenges and Solution for 45nm and Beyond”

by Dr. Haifang Liao, Celesda Design Solutions Inc.

Presentation available in pdf

Abstract: The advanced semiconductor technology provides the capability to integrate billions of transistors for SOC designs, the tape-out data for manufacture reaches terabyte magnitude, and the complexity of design rules in the deep sub-wavelength processes increases explosively. This talk will review challenges of physical verification for complicated SOC designs on 45nm process and beyond. We analyze properties of various applications in different aspects, complexity of design rules and layout structures, and introduce a fast platform for physical verification as well as design-for-manufacture (DFM) to analyze, verify, modify and optimize designs. The new solution is fully compatible with the existing design flow and offers multiple times speed up with signoff quality.

Bio: Haifang Liao received his B.S. and M.S degrees in electrical engineering from Zhejiang University in 1983 and Shanghai Jiao Tong University in 1986, respectively, and his Ph.D. degree in computer engineering from the University of California at Santa Cruz in 1995.

Dr. Liao is the CEO of Celesda Design Solutions, Inc. which he founded in 2008. Prior to that, he was the founder and CEO of eTop Design Technology, Inc. which was acquired by Cadence in 2004. Then in Cadence, he served as the senior architect and later the product manager of the physical verification. Before that, Dr. Liao was co-founder and VP engineering of Ultima Interconnect Technology, Inc., one of two predecessor companies to Celestry. Celestry was acquired by Cadence in 2003.

From 1986 to 1991, Dr. Liao was the lecturer in Shanghai Jiao Tong University. Among this period, from 1988 to 1990, he served as a manager to develop physical verification tool set for China national ICCAD project — Panda system.

“Wearable Respiratory Monitoring: Algorithms and System Design”

by Prof. Wee Ser, Nanyang Technological University

Presentation available in pdf

Abstract: More than 15% of the population suffers from some forms of respiratory disorders (e.g. Asthma, Bronchitis, Sleep Apnea, etc.) and some of such disorders can be acute. Currently, physicians perform such diagnosis by listening to lung sound using a stethoscope. The problem of this existing approach is that, the history of occurrence is important and yet patients’ descriptions are often erroneous. Furthermore, auscultation with stethoscope is subjective and cannot be used for long-duration monitoring too. The emerging trend is therefore to monitor respiratory disorders in a home setting through the use of a wearable system. This lecture will focus on presenting the findings generated from a joint research program undertaken by the lecturer and his engineering team at NTU and the physicians at the National University Hospital (Singapore). In particular, sound based monitoring of the respiratory disorders relating to wheezes (e.g. Asthma, COPD) will be discussed. In addition to presenting the typical characteristics of such signals, the lecture will also address the problems imposed by the wearable constraint and discuss the algorithms and system solutions to these problems. The development of algorithms and the associated circuits and systems has evolved through three generations of designs. The problems faced and the findings obtained for these designs will be shared at the lecture. A demonstration of the effectiveness of some of these techniques and designs will be given during the lecture too.

Bio: Dr. Wee Ser received his Ph.D. degree in Electrical and Electronic Engineering in 1982. He joined the Defence Science Organization (DSO) in 1982. He became the Head of the Communications Research Division in 1993 and was appointed Technological Advisor to the CEO of DSO National Laboratories in 1996. In 1997, he joined the Nanyang Technological University (NTU) as an associate professor and has since been appointed Director of the Centre for Signal Processing. Wee Ser is currently the associate editors for the IEEE Communications Letters and the Journal of Multidimensional Systems and Signal Processing (Springer), an IEEE CAS DL for 2010 and 2011, and a TC member in the IEEE CAS society. In 2009, he was the keynote speaker for the IEEE ICSIPA (International Conference Signal and Image Processing Application). Over the years, Wee Ser has served in various positions in IEEE activities and international conferences including being Chair of the IEEE Signal Processing Chapter (Singapore), international advisory committees, panel chair, TPC and track chairs of several IEEE international conferences. He has also served in several national advisory and technical committees and he is a board director of a public listed company. Wee Ser has published more than140 research papers in refereed international journals and conferences. He holds nine patents and is a co-author of six book chapters. He is the Principal Investigator of several externally funded research projects, and a regular reviewer of research grant proposals too. Wee Ser has received several prizes and awards, including best paper award, technology prize and competition award. His research interests include microphone array research, wearable signal processing system design; signal classification techniques, and channel estimation and equalization.

“Video Compression Technology – On Building the Next Generation”

by Prof. Nam Ling, Santa Clara University

Abstract: In recent years, significant increase in visual resolution and perceptual quality emerged. Another level of resolution and quality will be expected for home and mobile video applications as future devices and content move toward high definition (for mobile applications) and ultra-high definition (for home applications). Existing AVC/H.264 video compression technology will soon be unable to efficiently meet the compression demand for transmission. With the recent work from the Joint Collaborative Team on Video Coding (JCT VC) High Efficiency VideoCoding (HEVC) project, a new generation of video compression standardization process aiming at major improvements over the current AVC/H.264 standard has already begun. In this talk, we will briefly look at the expectation and the building of the technology for next generation video compression; we will also highlight our experience and work in this area.

Bio: Nam Ling received B.Eng. from Singapore, and M.S. and Ph.D. degrees from U.S.A. Since 2010, he is the Sanfilippo Family Chair Professor of Santa Clara University and the Chair of its Department of Computer Engineering. He was an Associate Dean (Graduate Studies, Research, and Faculty Development) for its School of Engineering during 2002-2010. Currently he is also Consulting Professor for the National University of Singapore and Guest Professor for Shanghai Jiao Tong University. Dr. Ling is an IEEE Fellow for contributions to video coding algorithms and architectures. He is also an IET Fellow. He has more than 150 publications and standards contributions, including a book. He was named IEEE Distinguished Lecturer twice and received the IEEE ICCE Best Paper Award (First Place). He received four major awards from the University (Outstanding Achievement, Recent Achievement in Scholarship, President’s Recognition, and Sustained Excellence in Scholarship) and two awards from its Engineering School (Researcher of the Year and Teaching Excellence). He served as Keynote Speaker (IEEE APCCAS, VCVP, JCPC, and will be for the coming IEEE ICAST and ICIEA), Distinguished Speaker (IEEE ICIEA), General Chair/Co Chair (IEEE Hot Chips, VCVP), Technical Program Co Chair (IEEE ISCAS, APSIPA ASC, IEEE APCCAS, IEEE SiPS, DCV), and Technical Committee Chair (IEEE CASCOM TC and TCMM). He also served as Guest Editor/Associate Editor for journals (IEEE TCAS I, JSPS) and delivered more than 110 invited colloquia worldwide.

“ISSCC 2011 talks”

First talk: “A 65nm Dual-Band 3-Stream 802.11n MIMO WLAN SoC” by Dr. Shahram Abdollahi-Alibeik, Qualcomm Atheros

Abstract: An 802.11n 3-stream 3×3 MIMO WLAN SoC, incorporating three transceivers, is implemented in 65nm CMOS with a die area of 22mm2. The design employs on-chip IQ mismatch calibration and a reference clock doubler to achieve an EVM floor of -39dB/-36dB at 2.4/5GHz.

Bio: Shahram Abdollahi Alibeik received the B.S. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1993 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1996 and 2001, respectively. From 2001 to 2003, he was with T-RAM, Inc., designing analog and critical path custom digital circuits for memory ICs. Since September 2003, he has been with Atheros Communications, now Qualcomm Atheros, working on analog, mixed-signal and RF circuits.

Second talk: “A 10Gb/s Half-UI IIR-Tap Transmitter in 40nm CMOS” by Halil Cirit, NetLogic Microsystems

Abstract: A transmit equalizer is designed for 10-Gb/s serial communication and features half-UI, IIR and FIR taps. Both SFI transmitter waveform dispersion penalty (TWDPc for direct-attach copper cable) and data-dependent jitter (DDJ) specifications are met with a single transmitter configuration. The circuit, fabricated in 40-nm CMOS, dissipates 125 mW and occupies 0.22 mm².

Bio: Halil Cirit received the BSEE degree from Haceteppe University in Ankara, Turkey. He received the MSEE degree from Santa Clara University. From 2005 to 2008 he was a mixed-signal design engineer at nVidia Corp. Since 2008 he has been with the Physical Layer products group at NetLogic Microsystems engaged in circuit design for 10-Gb/s and 100-Gb/s Ethernet products.

“Reliability and Yield of MOS Devices and Circuits”

by Prof. Gilson Wirth, Universidade Federal do Rio Grande do Sul

Presentation available in pdf

Abstract: With the device sizes shrinking well below 100 nm and introduction of novel materials in the fabrication technology, new phenomena started playing a role on the reliability of MOS devices. As a consequence, performance and reliability become influenced also by factors other than physical dimensions. We need to understand the underlying physical mechanisms, and develop analysis and modeling techniques to support IC designers. Furthermore, the variations of parameters over time (aging and transient effects such as noise and soft errors) may lead to dramatically increased overhead in the timing budget, as well as on test procedures.

Effects that play a major role on the reliability of today digital and analog designs are discussed, as well as effects that are expected to become relevant in future technologies.

Modeling techniques to abstract the physical level effects into the design flow are studied.

Among the effects discussed, the major ones are:

– Parametric variability due to effects such as random dopant fluctuations and line edge roughness.

– Aging effects such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Electromigration and Time Dependent Dielectric Breakdown (TDDB).

– Radiation Effects as Single Event Transients (SET) and Single Event Upsets (SEU).

– Device intrinsic noise, with focus on the Random Telegraph Signal (RTS). Besides its importance for analog design, as a source of low-frequency noise, RTS is also becoming a concern in digital circuits, as for instance in SRAM and flash memories. RTS may be modeled as momentary changes in threshold voltage, meaning that circuit behavior may change between two logic operations of a digital circuit. Different modeling approaches are discussed, focusing on operation conditions relevant for digital and analog design, including large signal AC operation.

Design techniques to improve yield and reliability are also addressed.

Mutual relation between the different reliability phenomena is also studied. For instance, charge trapping and de-trapping plays a role in both bias temperature instability and low-frequency noise, and random dopant fluctuations may exacerbate the impact of BTI and noise on circuit performance.

Bio: Gilson I. Wirth received the B.S.E.E and M.Sc. degrees from UFRGS, Brazil, in 1990 and 1994, respectively. In 1999 he received the Dr.-Ing. degree in Electrical Engineering from the University of Dortmund, Dortmund, Germany.

He is currently a full professor at the Electrical Engineering Department at the Universidade Federal do Rio Grande do Sul – UFRGS.

From July 2002 to December 2006 he was professor and head of the Computer Engineering Department, Universidade Estadual do Rio Grande do Sul (UERGS). In July, August and December 2001 he was at Motorola, Austin, Texas, leading the team working in CMOS process technology transfer to CEITEC, Porto Alegre, Brazil. In February and March 2002 he was at the Corporate Research Department of Infineon Technologies, Munich, Germany, working as guest researcher on low-frequency noise in deep submicron MOS devices.

His research interests include low-frequency noise, ionizing radiation effects, bias temperature instability (BTI), reliability and design for yield of digital, analog and mixed-signal circuits.

An updated list of publication may be found at http://lattes.cnpq.br/1745194055679908.