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2015 Events

Better Broadband Transmitters with RF-DACs

Date: January 14th, 2015

When: 6:30pm – 8:45pm

Where: Texas Instruments Building E, 2900 Semiconductor Dr., Santa Clara, CA 95051 (See Map)

IEEE SCV CAS cosponsors IEEE SCV Communications Society on a technical talk

Registration Link is available here

Session Abstract:Moving RF-modulation, filtering and channel combining into the digital domain has recently enabled an order of magnitude power and size reductions in cable head end equipment. Small modules on a single line card have replaced racks of cable head-end equipment needed to supply video and high speed data to our homes. The key to this revolution is the use of RF D/A-Conversion. RF-DACs enable small, low power, GHz bandwidth RF transmitters with good spectral purity and high order modulation schemes to be designed. As end user demand for bandwidth continues to grow driving increased bandwidth in access networks RF-DACs are finding applications beyond cable. We will discuss RF-DACs, their function and their application in the design of highly flexible RF transmitters with wide bandwidths, small form factors and low power.

Speaker: Kurt Rentel

Bio: Kurt R. Rentel received the BS degree in Electrical Engineering from Iowa State University in 1979 and received the MS degree in Electrical Engineering from Colorado State University in 1984. He has been in a range of positions in design, business development, and marketing at Hewlett Packard, Comlinear, National Semiconductor and Maxim Integrated. He is currently Executive Director of Business Management for communication products at Maxim. He has been involved in analog and mixed signal solutions for broadband communications systems throughout his career with a focus on high speed ADCs and DACs.

Speaker: Geir Ostrem

Bio: Geir S. Ostrem (M’89) is leading communications infrastructure IC design at Maxim Integrated, Colorado Springs, Colorado. He received the M.Sc. and Ph. D. degrees in electrical engineering from the Norwegian University of Science and Technology in Trondheim, Norway in 1991 and 1996 respectively. He designed analog CMOS, BiCMOS and bipolar ASICs for a multitude of applications at Nordic VLSI, Trondheim, Norway from 1992-1998, with primary focus on high speed ADCs. From 1998 to 1999, he contributed to an analog front end for ADSL at Globespan Semiconductor, Red Bank, New Jersey as an LSI design project lead. He designed high speed ADCs at Signal Processing Technologies, Colorado Springs, Colorado from 1999 to 2001. Since 2001 he has been with Maxim Integrated, where his main contribution has been the development of RF-DACs, eliminating analog modulators in wired and wireless RF transmitters. Currently, he is an Executive Director of IC Design. His work is focused on digital RF solutions.

FIRST Program for High School Robotics Competition.

Date: February 2nd, 2015

Location: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA

High School Team: Event Horizon, FRC team #5027 Andrew Hill High School, San Jose, California.

The Robotics team from Andrew Hill High School in San Jose (East Side Union High School District) will discuss their robot, their team and their experiences with designing competition robots. They will be led by their team president Tina Nguyen, and supported by one of their Mentor’s IEEE CAS member Jonathan David. Chip, the Robot used in the 2014 competition will be demonstrated.

This event is in support of the CAS outreach program, as we hope some of these students will become IEEE members, and CAS members once they get to College.

IEEE SCV CAS officer Elections will be also be held at this meeting.

The Human Intranet – Where Swarms and Humans Meet

Date: February 17th, 2015

This event is sponsored by the IEEE Computer Society.  It is being co-sponsored by both the Circuits and Systems Society, the Solid State Circuits Society and the Signal Processing Society.

Location: Cadence / Bldg 10, 2655 Seely Ave, San Jose, CA (map)
Speaker: Dr. Jan M. Rabaey, Professor, UC Berkeley
Time: 6:30 PM (PT) Networking/Refreshments, 7:00 PM Presentation

Presentation available for download here: pdf

There is no question about it – the Internet of Things (IoT) is happening as we speak. It is radically transforming the information technology platform, and providing an extremely high bandwidth channel between the cyber world (as represented by the Cloud) and the physical and biological world in which we live. The evolution is quite foundational as for the first time it allows for the engineering of systems that tightly interweave the “real” physical and the “imaginary” cyber worlds, often blurring the boundary between the two.

Yet, the IoT concept on itself conjures a picture of a static, internet-centric organization, in contrast to the dynamic and organic nature of many of the cyber-{physical,biological}
applications we envision. In such an environment, which we have dubbed the “Swarm”, applications would form by opportunistically marshaling the resources that are available to them at a given time and place. The Berkeley Ubiquitous Swarm Lab is developing a broad range of technologies essential to make the Swarm vision come to reality.

Some of most compelling application domains of the Swarm relate to how humans interact with the world around it and the cyberworld beyond, as well as their fellow human beings and themselves. While the smartphone has already introduced a fundamental change, most of our interactions are still funneled through a limited set of means (such as displays, headphones, keyboards, touch panels) integrated in a single device. The Swarm has the potential to change all of this. Envision instead a “Human Intranet”, that harvests the capabilities of all the devices we carry around us, on us, or inside us, to create a single open and integrated platform, opening the door for true innovation and creativity.

In this presentation, some of the true opportunities, challenges and limitations of the swarm and human intranet vision will be addressed.

Dr. Jan Rabaey received the EE and Ph.D. degrees in Applied Sciences from the Katholieke Universiteit Leuven, Belgium, in 1978 and 1983 respectively. From 1983-1985, he was a Visiting Research Engineer at UC Berkeley. From 1985-1987, he was a research manager at IMEC, Belgium, and in 1987, joined the faculty of the Electrical Engineering and Computer Science department at UC Berkeley, where he is now holds the Donald O. Pederson Distinguished Professorship. He has been a visiting professor at the University of Pavia (Italy), Waseda University (Japan), the Technical University Delft (Netherlands), Victoria Technical University and the University of New South Wales (Australia). He was the Associate Chair (EE) of the EECS Dept. at Berkeley from 1999 until 2002 and is currently the Scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the director of the Multiscale Systems Research Center (MuSyC).

Professor Rabaey has authored or co-authored a wide range of papers in the area of signal processing and design automation. He has received numerous scientific awards, including the 1985 IEEE Transactions on Computer Aided Design Best Paper Award (Circuits and Systems Society), the 1989 Presidential Young Investigator award, and the 1994 Signal Processing Society Senior Award. In 1995, he became an IEEE Fellow. He has also be awarded the 2002 ISSCC Jack Raper Award, the 2008 IEEE Circuits and Systems Mac Van Valkenburg Award, the 2009 EDAA Lifetime Achievement Award, and the 2010 Semiconductor Industry Association University Researcher Award. In 2011, he was elected to the Royal Flemish Academy of Arts and Sciences (Belgium). He is past Chair of the VLSI Signal Processing Technical Committee of the Signal Processing Society and has chaired the executive committee of the Design Automation Conference. He serves on the Technical Advisory Boards of a wide range of companies.

Shannon-inspired Statistical Computing

Date: February 27th, 2015

Event sponsored by the IEEE Solid State Circuit Society, IEEE Circuits and Systems Society is a cosponsor.

Where: Jack Gifford Event Center, Maxim Integrated Products Headquarters, 160 Rio Robles, San Jose, CA 95134

When: Friday, February 27th, 2015, 4:30PM – 6:30PM

Networking and Refreshments ($5 donation required) 4:30PM – 5:00PM, Technical Talk 5:00PM – 6:30PM

Speaker: Mr. Naresh R. Shanbhag, University of Illinois at Urbana-Champaign


Moore’s Law has been the driving force behind the exponential growth in the semiconductor industry for the past five decades. Today, energy efficiency and reliability challenges in nanoscale CMOS (and beyond CMOS) processes threaten the continuation of Moore’s Law. This talk will describe our work on developing a Shannon-inspired statistical information processing that seeks to address this issue by treating the problem of computing on unreliable devices and circuits as one of information transfer over an unreliable/noisy channel. Such a paradigm seeks to transform computing from its von Neumann roots in data processing to Shannon-inspired information processing. Key elements of this paradigm are the use of statistical signal processing, machine learning principles, equalization and error-control, for designing error-resilient on-chip computation, communication, storage, and mixed-signal analog front-ends. The talk will provide a historical perspective and demonstrate examples of Shannon-inspired designs of on-chip subsystems. This talk will conclude with a brief overview of the Systems On Nanoscale Information fabriCs (SONIC) Center, a multi-university research center based at the University of Illinois at Urbana-Champaign, focused on developing a Shannon/brain-inspired foundation for information processing on CMOS and beyond CMOS nanoscale fabrics.

Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His research interests are in the design of robust and energy-efficient integrated circuits and systems for communications including VLSI architectures for error-control coding, and equalization, noise-tolerant integrated circuit design, error-resilient architectures and systems, and system-assisted mixed-signal design. Dr. Shanbhag received the 2010 Richard Newton GSRC Industrial Impact Award, became an IEEE Fellow in 2006, received the 2006 IEEE Journal of Solid-State Circuits Best Paper Award, the 2001 IEEE Transactions on VLSI Best Paper Award, the 1999 IEEE Leon K. Kirchmayer Best Paper Award, the 1999 Xerox Faculty Award, the Distinguished Lecturership from the IEEE Circuits and Systems Society in 1997, the National Science Foundation CAREER Award in 1996, and the 1994 Darlington Best Paper Award from the IEEE Circuits and Systems Society.

Dr. Shanbhag is serving as an Associate Editor for the IEEE Journal on Exploratory Solid-State Computation Devices and Circuits (2014-16), served as an Associate Editor for the IEEE Transaction on Circuits and Systems: Part II (97-99) and the IEEE Transactions on VLSI (99-02 and 09-11), respectively. He was the General Chair of the 2013 IEEE Workshop on Signal Processing Systems, the General co-Chair of the 2012 IEEE International Symposium on Low-Power Design (ISLPED), the Technical Program co-Chair of the 2010 ISLPED, and served on the technical program (wireline subcommittee) committee of the International Solid-State Circuits Conference (ISSCC) from 2007-11. Since January 2013, he is the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi-university center funded by DARPA and SRC under the STARnet phase of FCRP. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of Intersymbol Communications, Inc., a venture-funded fabless semiconductor start-up that provides DSP-enhanced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links. In 2007, Intersymbol Communications, Inc., was acquired by Finisar Corporation, Inc..

EFLX: an FPGA IP core for SoCs

Date: March 16th, 2015

Speaker: Dr. Cheng C. Wang, Flex Logix Technologies, Inc.

Cheng C. Wang, VP of Engineering of Flex Logix Technologies, Inc, will present on their IP technology for an embedded FPGA core for your SoC. The physical IP is a full-functioned FPGA, ranging from 100 LUTs to more than 300K LUTs, currently offered for TSMC28HPM, but portable to any process in 2-3 months. This talk will highlight the award-winning EFLX FPGA technology, its specifications, software flow, and applications.

Cheng C. Wang received his B.S. in EECS with High Honors from University of California, Berkeley in 2005, his M.S. and Ph.D. in EE from University of California, Los Angeles in 2009 and 2013, respectively. He is the recipient of the 2013 Outstanding PhD Dissertation Award from UCLA Electrical Engineering and the 2014 Lewis Award for Outstanding Paper from ISSCC.

Realizing the next growth wave for semiconductors – A new approach to enable innovative startups

Date: April 29th, 2015


7:00-7:30pm Networking & Refreshments

7:30-8:30pm Talk, Q&A

IEEE SCV CAS cosponsors IEEE SCV PACE on a technical talk.

Registration link is available here.

Cost Free.  Food donation accepted: $3 for IEEE members, $5 for non-IEEE members


Daniel Armbrust, CEO and co-founder, Silicon Catalyst


The semiconductor industry has evolved from its early days of startups and spinouts financed by venture capital to an era of specialization associated with the rise of foundries and fabless companies to today’s structure characterized by consolidation and dominance by a few leaders in each of the product areas. Looking forward, there is anticipation that a new wave of innovation associated with key trends in energy, personal health care, autonomous transportation, mobility, and home automation, generally referred to as the Internet of Things (IoT), is upon us.

To realize these optimistic expectations for meaningful growth, innovation and entrepreneurship generally associated with startups will be even more crucial. However, all of the indicators ranging from IPO’s, venture capital investment, and organic industry growth rates strongly suggest that new business models are needed. Taking inspiration from the robust incubation and acquisition activities in software and biotech, a new approach to assist startups pursuing solutions in silicon is being pursued. Its unique focus is on the difficult problems entrepreneurs and new companies encounter when attempting to innovate in semiconductors … namely the challenge of raising sufficient funding and obtaining the appropriate design, prototyping, and test capabilities to move from concept to working prototypes.

In this context, a new early-stage startup incubator called Silicon Catalyst is being launched. The objective is to stimulate a vital and robust startup community by connecting the interests of the industry stakeholders, ranging from systems and product-based companies to the enabling supply chain to a network of mentors experienced in assisting startups, and to investors who are looking for attractive returns and timely graduation and acquisition.

This presentation will describe the key financial and innovation trends of the semiconductor industry, whose advances underpin a broad set of industries that depend on ever more useful and cost-effective electronics. For context, comparisons with the structure and evolution of related industries will be made. Building upon this framework, the business model and novel approach using lean innovation principles that is being taken by Silicon Catalyst will be described in context of the global trends emerging from extending Moore’s law over the next decade and driving innovations for the next IoT growth wave.


Daniel Armbrust is CEO of Silicon Catalyst, the industry’s first incubator for semiconductor solutions startups.  Silicon Catalyst is addressing the challenges faced by early stage start-ups progressing from concept to prototype by providing funding, mentoring and technical services from industry stakeholders. Silicon Catalyst is proud to have Synopsys, TSMC and Keysight as its founding partners.  Silicon Catalyst’s initial location is in Silicon Valley and expects to collaborate with regional partners to support innovative semiconductor startups globally.  Armbrust is responsible for recruiting strategic partners to invest and mentor a portfolio of innovative startups and develop them for further seed investment or acquisition.

He most recently served as President and Chief Executive Officer of SEMATECH from 2009 until April of 2014, with the responsibility to lead the consortium’s advanced technology R&D programs in lithography, front-end processes, interconnect, metrology, and SEMATECH’s manufacturing collaboration initiative International SEMATECH Manufacturing Initiative (ISMI).  During his tenure, SEMATECH significantly expanded its membership and contributions throughout the supply chain including materials, equipment, packaging, fabless and EDA companies.  In addition, SEMATECH renewed its partnership with New York State and CNSE as a integral component of its funding model.

Armbrust previously held various technical, management and executive positions for over 25 years at IBM, culminating in his tenure as Vice President of 300mm Semiconductor Operations where he was responsible for the operation of IBM’s 300mm fab in East Fishkill, New York, which develops leading edge technologies with IBM’s alliance partners and manufactures products for IBM and OEM customers.  His leadership was marked by successful efforts to improve operating efficiency, establish and lead collaborations within the industry, and build strong technical teams.

Prior to his role as Vice President, Armbrust served as Director of 300mm Engineering and Strategic Client Executive for IBM’s Systems and Technology Group.  He began his career at IBM in 1983 and progressed through a variety of assignments in process development, manufacturing and client engagement.

Armbrust earned a bachelor’s degree in ceramic science and engineering from Pennsylvania State University as well as a master’s of science degree in manufacturing systems engineering from Rensselaer Polytechnic Institute. 

Contact information:

IEEE MTT-SCV Short Course 2015, Co-sponsored by IEEE SCV CAS – RF, EMI/EMC and Gigabit HSS: Instrumentation, Components and Practice

Date: October 17th, 2015

Please join IEEE Microwave Theory and Techniques Santa Clara Valley Chapter (MTT-SCV) and IEEE Circuits and Systems Santa Clara Valley Chaper (SCV CAS) for this exciting full day short course and training.

Location: Santa Clara Convention Center, Great America Rooms 1 and 25001 Great America Pkwy, Santa Clara, California, United States 95054 (map)

Time: 8:00am-6:30pm PST (10.50 hours)

Registration cost: $20 (including meals and receptions)  Click Here to Register

OverviewDuring this one-day conference, a practical overview of the fundamentals of RF technology such as Maxwell’s equations, electromagnetic theory, and S-parameter methods will be presented. Examples and illustrations are designed to convey RF and the closely related EMI/EMC concepts in an understandable format that will appeal to students, engineers entering the industry, as well as experienced practicing engineers wanting to brush-up on the fundamentals.  Time and frequency domain measurement techniques will be presented, and live demonstrations of instrumentation will be given. Key components (amplifier, filter, and mixer) utilized in the RF and EMC world will be discussed, and tied in to the measurements by going down the data sheet specifications for each to show how the measurements are reliably done. The course will also include an expo with local sponsors giving hands-on demonstrations of instruments and components.

Schedule: (for updated sponsor list and agenda see short course website)




Registration and Breakfast (Continental)


Welcome Greeting


Microwave Engineering: What is it, where is it headed, and how it serves the mankind – Professor Madhu Gupta, Distinguished Microwave Lecturer




Core Foundation: S-parameters, Electromagnetic Fields – Orin Laney


Passive Components: Directional Couplers, Signal Dividers, Filters, Circulators, Hybrids – Professor Ramesh Abhari


Lunch and Expo


Active Components and Systems: Mixers, Filters, LNA, PA – Dr. Earl McCune




Test & Measurement: Fundamentals and Equipment Demonstrations – Orin Laney


Active Reception, Q&A, Expo, and Hands-On Equipment Interaction


Madhu S. Gupta: received the Ph.D. degree in Electrical Engineering from the University of Michigan, Ann Arbor, and is presently both an Adjunct Professor of Electrical & Computer Engineering at University of California, San Diego and the RF Communications Systems Industry Chair Professor at San Diego State University. Along with his other technical interests, his work concerns noise and fluctuations in devices that are active, nonlinear, very small, or used in high-speed/high-frequency applications. Dr. Gupta is an IEEE Fellow; has served as the Editor of IEEE Microwave and Guided Wave Letters and IEEE Microwave Magazine and of three IEEE Press books; has been a conference organizer and Chair of Technical program Committee of IMS2010; and has received the 2008 Distinguished Microwave Educator Award from IEEE Microwave Theory & Techniques Society in addition to a number of awards for outstanding teaching. Dr. Gupta served as the President of the IEEE Microwave Theory & Techniques Society in 2013, and is currently a Distinguished Microwave Lecturer. He firmly believes that every technical talk should be entertaining, enlightening, and inspiring.

Earl McCune: received his BS/EECS degree from UC Berkeley, his MSEE (Radioscience) from Stanford University, and his Ph.D. from UC Davis in 1979, 1983, and 1998 respectively. He is a serial Silicon Valley entrepreneur, founding two successful start-up companies since 1986: Digital RF Solutions (1986-1991, merged with Proxim) and Tropian (1996 – 2006, acquired by Panasonic). He is now retired from his position as a Technology Fellow of Panasonic, and is an author, instructor, and independent consultant. He is currently an instructor for Besser Associates for both Practical Digital Wireless Signals and Frequency Synthesis Principles. He holds 58 issued US patents, and is the author of Practical Digital Wireless Signals (Cambridge 2010).

In his nearly 40 years of experience in the wireless communications industry he has worked in areas including technology development, circuit design, along with systems architecture and integration. This experience has been gained at NASA, Hewlett Packard, Watkins-Johnson, Cushman Electronics, Digital RF Solutions, Proxim, Tropian, and Panasonic. The start-up Digital RF Solutions pioneered modulated direct digital synthesis (DDS) technology for very high dynamic range transmitters. Tropian developed and implemented envelope tracking and polar modulation techniques for highly efficient, multiband and multi-mode linearized power amplifiers.

Orin Laney: is an independent consultant in Mountain View, California.  He holds an MSEE from San Jose State University, an MBA from Brigham Young University, iNARTE certification as an EMC Engineer, and is a California licensed PE.  Mr. Laney is a National Speaker for IEEE-USA and has presented at over 100 campuses, has served as an expert witness, and is a published author, seminar instructor, and courseware developer. Over the years he has taught many courses in design for EMC regulatory compliance, design for signal integrity, and the theory and application of TDRs, VNAs, BERTs, etc.

With over 40 years of experience in mixed-signal design, Mr. Laney consults in RF Instrumentation, high-speed circuitry, and design for SI and EMC compliance. Projects include ultrasonic and optical imaging, instrumentation and telemetry, inductor and transformer design, specialty and miniature (endoscopic) video cameras, analog and HD video processing, and power conversion. His designs have been used in many industries, such as medical equipment, Hollywood special effects, and aerospace and defense requirements. Design requirements have ranged from microvolt level, sub-hertz hydrophone instrumentation to hardening against microwave fields in excess of 20kV/m. Many cross-disciplinary projects have involved optics, acoustics, mechanics, and other technologies.

Ramesh Abhari: is a professor at Santa Clara University with research interests in antennas, signal/power integrity, high-speed interconnects, and microwave & mm-wave circuits. She received her Ph.D. in Electrical and Computer Engineering from the University of Toronto, and served as the chairperson of IEEE Toronto Microwave Theory and Techniques (MTT), Antennas and Propagation (AP) and Electromagnetic Compatibility (EMC) joint chapter. She also received certificates of recognition and the IEEE Toronto Centennial Medal for her services as the chapter chair. She is the founder of IEEE Montreal Component Packaging and Manufacturing Technology (CPMT).

Dr. Abhari pioneered the application of the electromagnetic bandgap structures in suppression of the power/ground noise and received the student paper award at the IEEE International Microwave Symposium in June 2002 for this work. She has been the recipient of a number of fellowships such as IEEE MTT-S Graduate fellowship in 2000, Ontario Graduate Scholarships for four consecutive years and University of Toronto V.L. Henderson fellowship. Her students have received paper awards at International Symposium on Antenna Tech. and Applied Electromagnetics (Antem) 2006 and IEEE Electrical Performance and Electronic Packaging (EPEP) 2007 Conferences.

Dr. Abhari is a senior IEEE member and  a reviewer for IEEE conferences and Transactions papers such as Trans. on Advanced Packaging, Trans. on Microwave Theory and Techniques, Trans. on Antennas and Propagation, IEE Proceedings on Microwaves, Antennas and Propagation, and Canadian Granting agencies. She is also a member of the technical committee of IEEE Workshop on Signal Propagation on Interconnects and IEEE EMC TC-10 Signal Integrity Committee.

Sub-Sampling PLL Techniques (CICC 2015 invited review paper)

Date: October 19th, 2015

LocationQualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA

Time: 6:30pm-8:15pm

Registration Cost: Free. Click Here to RegisterFood donation accepted: $2 for IEEE member, $5 for non-IEEE member

Speaker: Dr. Xiang Gao, Marvell

Abstract  This is a review talk of the sub-sampling PLL technique. It will cover the development of the sub-sampling PLL architecture and its applications. This talked is based on the speaker’s IEEE Custom Integrated Circuits Conference (CICC) 2015 invited review paper.

Bio  Xiang Gao received the M.Sc. and Ph.D. degree in EE with cum laude from the University of Twente, The Netherlands, in 2006 and 2010 respectively. Since 2010, he has been with Marvell, Santa Clara, CA, working on RF and analog IC design for wireless communication systems. He is currently a design manager at Marvell and a TPC member of ISSCC and RFIC.


Presentation available in pdf

Chip and IP block-level verification of ESD networks in the ESDi product (with Live Demo)

Date: November 16th, 2015

LocationQualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA

Time: 6:30pm-8:15pm

Registration Cost: Free. Click Here to RegisterFood donation accepted: $2 for IEEE member, $5 for non-IEEE member

Speaker: Dr. Dündar Dumlugöl, CEO, Magwel NV.


In this paper we will describe how the ESDi product performs simulation based chip- and IP block-level verification of ESD networks from the layout using non-linear table models of ESD devices. Table models represent static I-V (current-voltage) curves directly obtained from TLP measurements. ESDi imports the full-chip layout from GDSII, identifies all the IO-pads/bumps, then extracts parasitic interconnect resistances in the main discharge paths of HBM ESD events. All point-to-point and point-to-multi point resistances are extracted and categorized. This is done by an intelligent pruning of the layout looking for main discharge paths that go from one pad/pin to another pad/pin over one or more ESD devices. Next, HBM or MM tests are executed on all or a selection of pad-to-pad combinations based on a sequential path search algorithm and a non-linear iterative simulation technique that accurately simulates snap-back behavior taking into account trigger voltages of ESD devices. Multiple parallel power clamps or parallel devices with different trigger voltages are accurately simulated taking into account interconnect resistances.

Finally ESDi performs electro-migration checks on all simulated tests and generates reports which can be easily navigated from clickable lists together with field data of current densities and IR-drops for graphical debugging. All this is done very efficiently on large-scale designs with hundreds of pads/pins utilizing large-scale parallel processing with 100 or more threads.


Dündar Dumlugöl has been CEO of Magwel NV since November 2004, where he managed the company from its initial start-up phase to a successful EDA company providing physical simulation and verification solutions for analog, mixed-signal, power management and digital ICs.

He has over 30 years of experience in the EDA industry managing market leading products such as Spectre circuit simulator and the Analog Artist mixed-signal products while he was at Cadence Design Systems. These products are now the industry standard for analog/mixed-signal design.

At CoWare Inc. he was VP of engineering responsible for all product development. While at CoWare he spearheaded the development of the SystemC language and its accompanying tool suite. He was chairman of the Language Work Group in the Open SystemC International Consortium that successfully launched SystemC as the new industry standard language for system design.

He also held VP of engineering positions at Antrim Design Systems and director of engineering position at Barcelona Design.

Dr. Dumlugöl has a Ph.D. (1986) in electrical engineering from the Katholieke Universiteit van Leuven, Belgium.


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