SF Bay Area Nanotechnology Council

IEEE

Archive for the ‘Online’ Category

Nov 12th, 2020: Online Symposium on Quantum Computing: Devices, Challenges and Applications

Wednesday, October 21st, 2020

IEEE SFBA Nanotechnology Council presents a symposium on Zoom! Join us for this one-day virtual conference!

When: Thurs Nov 12 – 8:30 AM to 3:30 PM Pacific Time (9am start)
Cost:
$5 – with discounts available (Limited free tickets for Students and Unemployed/In-Transition/Retirees)

Online Event! Register HERE ! Registered attendees will receive an email with a link for the Zoom meeting

Quantum Computing: Devices, Challenges and Applications

The conference brings together leading researchers at the cutting edge of Quantum Computing technology from academia, government lab and industry. Topics covered will include various approaches to building quantum devices including superconducting Qbits (Google, IBM), adiabatic annealing (DWave\NASA Ames), and Quantum Photonic approaches such as defects in semiconductors and single atom Qubits using ultra cold atoms (Stanford\UC Berkeley).

Apart from discussions on different device approaches to harnessing information based on the interactions of light and electrons, the conference will also cover important computational challenges in this field. Topics covered will include designing effective quantum algorithms, quantum supremacy, scalability, quantum-inspire. We will strive to provide an effective forum for conference participants to network and actively engage with the speakers.

Our Lineup (for full abstracts and bios, click here!) :

Sept 15th, 2020: The Era of Hyperscaling in Electronics

Tuesday, September 1st, 2020

The Era of Hyperscaling in Electronics

Prof.  Suman Datta, Stinson Chair Professor of Nanotechnology, University of Notre Dame

Tues Sept 15, 11:30 AM – 1:30 PM : Online Check-in 11:30 AM – 12 Noon; Seminar 12 Noon – 1:30 PM

Online (Zoom) FREE Event! Register HERE

Abstract: 

Heterogeneous Integration Fabric

In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach sub-10 nanometer, it is apparent that room for further scaling in the horizontal plane is running out. Further, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. In this talk, I will discuss how electronics is poised to enter a new, third, era of scaling – hyperscaling – in which resources are added in a flexible way when needed to meet the demands of data abundant workloads. This era will be driven by advances in embedded non-volatile memories, hybrid devices with merged logic and memory functionalities, monolithic three-dimensional integration, and heterogeneous integration techniques.

Biography:

Suman Datta is the Stinson Chair Professor of Nanotechnology in Department of Electrical Engineering at the University of Notre Dame. Prior to that, he was a Professor of Electrical Engineering at The Pennsylvania State University, University Park, from 2007 to 2011. From 1999 till 2007, he was in the Advanced Transistor Group at Intel Corporation, Hillsboro, where he developed several generations of high-performance logic transistor technologies including high-k/metal gate, Tri-gate and non-silicon channel CMOS transistors. His research group focuses on emerging devices that enable new computing models. He is a recipient of the Intel Achievement Award (2003), the Intel Logic Technology Quality Award (2002), the Penn State Engineering Alumni Association (PSEAS) Outstanding Research Award (2012), the SEMI Award for North America (2012), IEEE Device Research Conference Best Paper Award (2010, 2011) and the PSEAS Premier Research Award (2015).  He is a Fellow of IEEE and the National Academy of Inventors (NAI). He has published over 350 journal and refereed conference papers and holds 185 patents related to semiconductors. He is the Director of a multi-university advanced microelectronics research center, called the ASCENT, funded by the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA). He will serve as the General Chair of the 2020 IEEE International Electron Device Meeting (IEDM).

August 6th, 2020: All-Printed Supercapacitors for In Space Manufacturing and Terrestrial Applications

Tuesday, July 28th, 2020

All-Printed Supercapacitors for In Space Manufacturing and Terrestrial Applications

Dr. Myeonglok Seol, NASA Ames Research Center

Aug 6, 2020, 11:30 AM – 1:30 PM : Online Check-in 11:30 AM – 12 Noon; Seminar 12 Noon – 1:30 PM

Online (Zoom) FREE Event! Register  Here!

ABSTRACT

Printing technology has evolved from traditional quick writing tools to the modern
manufacturing methods for functional devices and systems. The benefits of printing-based
manufacturing include less material waste, fast-turn around prototyping due to simple
design customization and wide substrate compatibility. In this presentation, all-printed
supercapacitors, where all the components are made by printing, are introduced. Because
the device is manufactured only by printing, the complexity of manufacturing facilities can
be minimized and the resource efficiency and versatility are maximized, which are
particularly important in places where the supply of material and human resources are
limited such as rural areas, environmental monitoring of nuclear sites and space exploration
missions. We have fabricated electrical double layer capacitors and pseudocapacitors, both
with high electrochemical performance and cyclic durability and the results will be discussed
in detail.

SPEAKER BIOGRAPHY

myeonglok seol speaker headshot

Myeonglok Seol is currently a Scientist at the Center for Nanotechnology at NASA Ames
Research Center. He received his PhD in Electrical Engineering from Korea Advanced
Institute of Science and Technology (KAIST) in 2016. His research focuses on energy
harvesting and storage devices, printed electronics, and nanotechnology-enabled devices.
He received Future Technology Leader Award from the Engineers’ Council in 2018 and the
2018 Mike Sargeant Career Achievement Award for Young Professionals from the Institute
of Engineering and Technology, IET (UK).

Relevant citations and links

M.-L. Seol et al., All-Printed In-Plane Supercapacitors by Sequential Additive Manufacturing Process, ACS Applied Energy Materials, 2020, 3, 4965-4973, https://pubs.acs.org/doi/abs/10.1021/acsaem.0c00510

[UPDATE – NOW VIRTUAL!] June 9th, 2020: Quantitative Plasmonic Sensing with Single-Chip Inkjet Dispense Surface Enhanced Raman Spectroscopy (ID-SERS)

Saturday, May 23rd, 2020

SFBA Nanotechnology Council is pleased to announce our first online seminar – and it’s free!

We’d also like to take a moment to appreciate our community – the Council has earned the 2019 IEEE Outstanding Chapter Santa Clara Valley, as well as the Nanotechnology Council Outstanding Chapter title worldwide. Please see the Awards page for details.  Thank you all for your support!

Now onto the talk!

——

Quantitative Plasmonic Sensing with Single-Chip Inkjet Dispense Surface Enhanced Raman Spectroscopy (ID-SERS)

Dr. Fausto D’Apuzzo, Optical Scientist, HP Labs

Tues June 9

Noon-1:30PM Pacific Time, Virtual Meeting via Zoom

Register Here ! (Note: FREE to attend, but limited to 100 attendees! Registration ends at 10AM Pacific Time June 2nd.)

drfaustoplasmonicsensing

ABSTRACT

In this talk, I will present our Laboratory work on highly-quantitative plasmonic sensing based on Surface Enhanced Raman Spectroscopy (SERS). I will first describe our nano-imprinted SERS substrate architecture and performance. Then I will show how inkjet dispensing can be used in conjunction with SERS to encode each sensor with a calibration pattern of microdroplets (~30 pico-liters), with the aim of locally calibrating sensor performance. This way, we demonstrate that Measurement Uncertainty of the SERS signal can be reduced below 2%, which to our knowledge, is a new record for plasmonic sensing platform. Furthermore, the use of inkjet dispensing in combination with Raman mapping improves assay throughput (100-fold) and reduces sample volume consumption (105-fold) in an automated and reproducible fashion. Since this approach overcomes important practical hurdles, we believe that this work reignites interest in the potential commercialization of plasmonic-based chemical sensors.

Recent paper for reference:  A Generalizable Single-Chip Calibration Method for Highly Quantitative SERS via Inkjet Dispense.

 

SPEAKER BIOGRAPHY

drfaustoheadshot

Dr. Fausto D’Apuzzo is Optical Scientist at HP Labs, working on the Life Science team. His research interests are in optics systems, plasmonics and metamaterials for bio-sensing, with a focus on Surface Enhanced Raman Spectroscopy (SERS). He started investigating plasmonic systems since his master (2011) and PhD at the University of Rome “Sapienza”, before holding a postdoc position at L. Berkeley National Labs (LBNL) studying 2D plasmonic systems with Synchrotron Nano-Spectroscopy. He interned as an Optical Engineer at ACAMP (Alberta, Canada) before joining HP Labs (2018-present) where he is developing plasmonic sensing systems for quantitative chemical analysis.