Atomic Layer Deposition of 2D Dichalcogenides at Wafer Scale

Dr. Thong Ngo, EMD Electronics

11:30 AM – 12:00 PM
Nano Journal Club
Lincoln Bourne
The following paper will be discussed: “Challenges for Nanoscale CMOS Logic Based on 2D Materials”
12:00 PM – 12:10 PM
Introduction; Announcements and Speaker Introduction
Glenn Friedman
12:10 PM – 12:55 PM
Thong Ngo
12:55 PM – 1:15 PM

Nano Journal Club (11:30 am – 12 noon) – Hosted by Lincoln Bourne

Nano Journal Club is hosting a discussion of the article titled:

Challenges for Nanoscale CMOS Logic Based on 2D Materials

Attendees are encouraged to participate in the Nano Journal Club discussion. You can access the paper using the embedded link.

Seminar (12:10 pm – 12:55 pm)

Atomic Layer Deposition of 2D Dichalcogenides at Wafer Scale
2D Transition metal dichalcogenide (TMD) materials have opened a route to continue the down-scaling trend of semiconductor technology.

The synthesis of conformal high quality 2D TMDs on 300 mm wafers is required to unlock the potential application of these materials in electronic devices. EMD Electronics is establishing a platform for TMD development using atomic layer deposition (ALD).

The talk will be focusing on 300 mm wafer-scale ALD deposition of TMD materials at temperatures ranging from 350 to 600 °C. The proposed ALD approach contributes to the efforts in developing high-quality 2D TMD materials that offer high performance and meet the down-scaling demand.

 In the past 3 years, Thong and the EMD Electronics Team at San Jose have been developing an ALD 2D materials platform focusing on TMDs for high mobility channel and Cu barrier/liner applications

Dr. Thong Ngo is an R&D engineer at EMD Electronics.

Thong finished his Ph.D. in Chemical Engineering from The University of Texas at Austin in 2015. His Ph.D. work explored functional crystalline oxides on Si and Ge for electronics using atomic layer deposition (ALD).

Thong joined Intermolecular Inc., a subsidiary of EMD Electronics, in 2015 where he has been working on materials process development, characterization, and integration for memory applications.