Conductive-bridge memory (CBRAM) with excellent high-temperature retention and tolerance to high levels of Gamma Radiation

gopinathTuesday December 17, 2013
Noon – 1  pm
Texas Instruments (TI) Auditorium E-1
2900 Semiconductor Drive
Santa Clara, CA








TITLE: Conductive-bridge memory (CBRAM) with excellent high-temperature retention and tolerance to high levels of Gamma Radiation

SPEAKER: Dr. Venkatesh P. Gopinath, V.P. of CBRAM Technology at Adesto Technologies

Development activities in resistive memories have undergone explosive growth in the past several years. Conductive-Bridge RAM (CBRAM) is a family of resistive memory that offers significant advantages of performance, cost, scaling and power as compared to today’s non-volatile memory technologies. While several implementations of RRAM technology have demonstrated excellent potential as next generation memory technology, the barriers to achieve commercial success remain rooted in overcoming process integration challenges as well as market and application requirements. Further, reliability and functional requirements for memory products vary depending on the end application for which they will be utilized.
This talk will focus on a family of fully CMOS integrated CBRAM technology that not only shows excellent performance and power advantages over today’s technologies but also demonstrates excellent high temperature (>200ºC) retention and tolerance to very high levels (5Mrad) of Gamma radiation. These features allow CBRAM to replace conventional NVM technology for traditional applications as well as solutions for operations under harsh operating conditions like automotive, medical (sterilization) and space applications.

Dr. Venkatesh (“P.G.”) Gopinath is the V.P. of CBRAM Technology at Adesto Technologies. His responsibilities include R&D and transferof CBRAM technologyto volume manufacturing. He has over 17 years of industry experience working on discrete and embedded memory technologies.He has held technical and managerial roles at LSI Logic, Sun Microsystems and Innovative Silicon. P.G.’s industrial experiences cover development and commercialization of conventional CMOS technologies as well as floating gate FLASH and floating body memory cells.He has over 30 granted patents and publications in various areas of semiconductor manufacturing.P.G. has a Ph. D. in Electrical Engineering from Michigan State Universityand an MBA from Santa Clara University.


  • 11:30 am – Registration & light lunch (pizza & drinks)
  • Noon – Presentation & Questions/Answers
  • 1:00 pm – Adjourn
COST: IEEE Members: $5, Non-members:$10

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