IEEE CEDA All Japan Join Chapter Seminar
Date/Time: 2015 April 16 (Thu) 15:10-16:10
Location: Tokyo Institute of Technology, Lecture Room S323@ 2F, South Bldg.3, Ookayama Cumpus
#35. South Bldg. 3
(1) Lecture: 15:10-16:10
Title: Logic Synthesis: Past and Future
Speaker: Dr. Alan Mishchenko (University of California at Berkeley)
This talk will review the development of logic synthesis from manipulating small Boolean functions using truth tables, through the discovery of efficient heuristic methods for sum-of-product minimization and algebraic factoring applicable to medium-sized circuits, to the present-day automated design flow, which can process digital designs with millions of logic gates. The talk will discuss the main computation engines and packages used in logic synthesis, such as circuit representation in the form of And-Inverter-Graphs, priority-cut-based technology mapping into standard-cells and lookup-tables, and don’t-care-based optimization using Boolean satisfiability. We will also address the importance of formal verification for validating the results produced by the synthesis tools, and explore deep synergy between algorithms and data-structures used in synthesis and verification. Finally, the presenter will share his 12-year experience of being part of an academic research group with close connections to companies in Silicon Valley, both design houses and CAD tool vendors.
Speaker’s bio: Alan Mishchenko graduated from Moscow Institute of Physics and Technology, Moscow, Russia, in 1993, and received his Ph.D. degree from Glushkov Institute of Cybernetics, Kiev, Ukraine, in 1997. In 2002, Alan started at University of California at Berkeley as Assistant Researcher. In 2013, he was promoted to Full Researcher. His research interests are in developing computationally efficient methods for logic synthesis and verification.
IEEE CEDA All Japan Joint Chapter
No Admission Charge.