IEEE Princeton Central Jersey Section

The relentless pace of Moore’s law has enabled rapid evolution of microprocessors performance with resulting dramatic increases in complexity. This talk will review some microprocessor design history and reflect on the speaker’s 40+ years of work in the semiconductor industry. Circuit innovation has been an important contributor delivering performance. However, the overriding requirement has been to deliver ever more complex high-quality designs on schedule to intercept the latest technology node. The goal of this talk will be to provide practical insights of value today and the future for engineers entering the field. Speaker(s): Bill Bowhill, Agenda: Presentation by Bill Bowhill: 12:00-1:00 PM Lunch and Reception: 1:00-2:30 PM Bldg: MIT Building 34, Grier Room A ( 34-401A), Cambridge, Massachusetts, United States, Virtual: https://events.vtools.ieee.org/m/436957

The number of connected devices is expected to reach 500 billion by 2030, which is 59-times larger than the expected world population. Objects will become the dominant users of next-generation communications and sensing at untethered, wireline-like broadband performance, bandwidths, and throughputs. This sub-terahertz 6G communication and sensing will integrate security and intelligence. It will enable a 10x to 100x increase in peak data rates. FPGAs are well positioned to enable intelligent radios for 6G when coupled with high-performance chiplets incorporating RF circuits, data converters, and digital baseband circuits incorporating machine learning and security. This talk presents use of 2.5D and 3D heterogeneous integration of FPGAs with chiplets, leveraging Intel’s EMIB/Foveros technologies with focus on one emerging application driver: FPGA-based 6G sub-THz intelligent wireless systems. Nano-, micro-, and macro-3D heterogeneous integration is summarized, and previous research in 2.5D chiplet integration with FPGAs is leveraged to forge a path towards new 3D-FPGA based 6G platforms. Challenges in antenna, packaging, power delivery, system architecture design, thermals, and integrated design methodologies/tools are briefly outlined. Opportunities to standardize die-to-die interfaces for modular integration of internal and external circuit IPs are also discussed. Speaker(s): Dr Farhana Sheikh, Agenda: 8pm - 9pm EST : DL and Q/A Virtual: https://events.vtools.ieee.org/m/420965

IEEE PCJS Fall ExCom Meeting. Agenda Follows Agenda: - Welcome note and Dinner - Chair/ViceChair/Treasurer/Secretary Report Out - Society/Chapter Report Out - Conference Report Out, - Open discussion Room: Room CS 105, 35 Olden Street, Princeton, New Jersey, United States, 08544, Virtual: https://events.vtools.ieee.org/m/440547

IEEE PCJS Broadcast Technology Society is excited to announce the following talk: Digital Television Standards and Their Worldwide Impact Guest Speaker: Glenn Reitmeier Location: Computer Science Building (CS 105) Princeton University, Princeton, NJ Event: October 28, 2024, starting at 7:00pm to 9:00pm Brief abstract of talk: The development of digital standards for broadcast television was a seminal event - it was a pivot from many decades of analog video technology to the world of digital media and video streaming that today's audiences enjoy all over the world. This talk will discuss the technical roots of analog video standards, how the quest for a high-definition broadcast television standard in the 1990s was met by a radical leap to digital technology, the world's first digital TV standard (ATSC), and the recent development of the ATSC 3.0 standard for internet based broadcasting and streaming. Also discussed will be the adoption of digital television standards throughout the world, how government regulators have managed to transition from analog to digital broadcasting and the commercial impact of standards on consumer electronics products from TVs to smart phones. Speaker Bio: Glenn Reitmeier is widely recognized as a technology visionary and pioneer in the television industry. Throughout his career, he has been a leader in establishing revolutionary new digital standards that are now widely used in video production and in content delivery by over-the-air broadcasting, satellite, cable and video streaming over the internet. Now an independent consultant, Glenn is retired from 17 years at NBC Universal as Senior Vice President, Technology Standards and Policy, where he contributed to industry technical standards and to the technical aspects of the company’s government policy positions and commercial agreements. Previously, Glenn spent 25 years in digital video research at RCA/Sarnoff Laboratories. In addition to leading Sarnoff’s work on digital HDTV, his laboratory also spun out six technology startup companies in digital television and media. Glenn has served the industry as a Board member of the Advanced Television Systems Committee (ATSC), the North American Broadcasters Associations (NABA) and the Open Authentication Technical Committee (OATC), and he has been Chairman of the Board of both ATSC and OATC. He is a SMPTE Fellow and a recipient of the Progress Medal and the Signal Processing Medal. He is also an inaugural member of the Consumer Technology Association’s (CTA) Academy of Digital Television Pioneers, a recipient of the National Association of Broadcasters (NAB) Television Engineering Award for lifetime achievement and a recipient of the ATSC’s Bernard J. Lechner Award for outstanding technical contributions. Glenn holds over 60 patents, has contributed to many Emmy award winning technologies and is recognized in the New Jersey Inventors Hall of Fame. He received his B.E.E from Villanova University and an M.S.E in Systems Engineering from the University of Pennsylvania. Bldg: Department of Computer Science (CS 105), Princeton University, 35 Olden Street, Princeton, New Jersey, United States, 08540

This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.5μS and 73 μS, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW Speaker(s): Sudipto Chakraborty, Agenda: Refreshments Distinguished Lecture Room: B205, Bldg: Engineering Quad, Olden Street, Princeton, New Jersey, United States, 08544

This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.5μS and 73 μS, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76x10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW Speaker(s): Sudipto Chakraborty, Agenda: Refreshments Distinguished Lecture Room: B205, Bldg: Engineering Quad, Olden Street, Princeton, New Jersey, United States, 08544

Join the IEEE Foundation on Friday, 8 November, at 11:30 a.m. EST for an IEEE Foundation Estate Planning Luncheon at the beautiful Bell Works venue in Holmdel, NJ. This event is an opportunity for IEEE Members and friends to gather and connect with peers before the holidays and to see how investing in the future could keep many of the IEEE activities and programs thriving for generations to come. Estate planning encompasses various components, and knowing which ones apply to you and the correct order in which to address them is essential. Often, people focus on reducing inheritance taxes at the expense of maximizing retirement cash flow and lowering effective tax rates. It is crucial to understand how properly structuring assets and cash flows can lead to increased retirement cash flow and reduced tax rates during your lifetime. Our keynote speaker is Shaun Scutellaro, CPA and Partner at Cohn Reznick, LLP. Shaun has extensive career experience in public and private accounting and domestic and foreign tax. He is a member of the AICPA and NJCPA and is beginning a term on the board of Trustees for NJCPA compliance for individuals. Shaun will guide us through his expertise in a brief and insightful seminar on estate planning. Event Details: Speaker: Shaun Scutellaro, CPA Moderated by: Danny DeLiberato Location: Bell Works 101 Crawfords Corner Rd Holmdel, NJ 07733 Quantum Room Date: 8 November 2024 Time: 11:30 a.m. Eastern Standard Time (https://secure.ieeefoundation.org/site/Calendar?id=100202&view=Detail) If you are unable to attend the scheduled event, you can still receive materials by visiting the (https://www.ieeefoundation.org/our-supporters/ieee-goldsmith-legacy-league/). For additional information, contact Laura Bessey, Donor Engagement Specialist, at donate@ieee.org or +1 732-465-7817. Warmest Regards, Joe Jesson Room: Quantum Room, Bldg: Bell Works, 101 Crawfords Corner Rd, Holmdel , New Jersey, United States, 07733

Welcome to the first session of the IEEE Princeton Central Jersey Section (PCJS) Data Analytics Group. As a Chair of this newly established group, I am excited to introduce a platform dedicated to fostering learning, collaboration, and growth in the rapidly evolving field of data analytics. This session is designed to welcome members, non-members, students, and aspiring data professionals, providing an overview of the fundamentals of data analytics and its growing significance across industries. We aim to offer valuable insights into how this group will serve as a community hub, bringing together industry experts to discuss current trends, key challenges, and emerging opportunities within the field of data analytics. Our mission is to empower learners at all levels by providing access to thought leaders, industry professionals, and real-world applications of data analytics. Attendees will gain a better understanding of the tools, techniques, and issues shaping the future of data analytics, as well as actionable strategies for advancing their skills and careers in this dynamic domain. This session marks the beginning of an ongoing conversation where we, as a community, will explore the limitless potential of data and how it can be harnessed to drive innovation and solve complex problems. Agenda: 6:00 PM - 6:30 PM : Pizza and Networking 6:30 PM - 7:30 PM : Talk 7:30 PM - 8:00 PM : Q/A and Wrap-up Room: Room CS 105, 35 Olden Street, Princeton, New Jersey, United States, 08544, Virtual: https://events.vtools.ieee.org/m/440552

With climate change already here and its effects all around us, it’s urgent to continue efforts across all industries to reduce CO2 emissions. But what about the information technology sector? The World-Wide Web we depend on enriches our lives in many areas: education, commerce, government, news, communication, and more. However, the infrastructure that enables it uses a lot of electricity — not all of which is generated from renewable resources (hence its CO2 generation.) Combining the fields of computers and the environment, a relatively new Website construction method called “Sustainable Web Design” is gaining awareness. This software-based approach reduces non-renewable energy to lower CO2 emissions so the people of today and tomorrow can benefit from everything that the Web offers. How a Website is constructed and presents its information has real-world effects! A Website can be built to serve smaller files, use less resources, and require less processing power — all of these help reduce non-renewable energy use and associated CO2 emissions. Sustainable Web Design also has side-benefits: a faster Website, better mobile device battery life, higher-placed mobile Google search results, and better accessibility. This presentation will introduce how to determine a Website’s sustainability, identify elements which can slow down a Web page, describe basic sustainable Web design strategies and techniques, offer easy to take actions and examples, present the perspective and advice of a Website Designer/Webmaster who remade his organization’s Website to be sustainable, and list additional resources to follow the latest developments. Speaker(s): , Michael Blank Room: 105, Bldg: Computer Science Building, 35 Olden St, Princeton, New Jersey, United States, 08544, Virtual: https://events.vtools.ieee.org/m/437519

IEEE PCJS Volunteers, spouses, local section leadership, Region 1 leaders and Awardees are invited to this Holiday Dinner. We will host this banquet at Mercer Oaks Golf Course in West Windsor, NJ on December 18. Bldg: Mercer Oaks Golf Club, 725 Village Road West, Princeton Junction, New Jersey, United States, 08550