“Process Integration and Reliability for Copper Interconnects in Low-k Dielectrics” by Jeffrey Gambino, PhD, IBM Microelectronics, Essex Junction, Vermont, USA.

Date:  August 25, 2011 (Thursday)
Time:  7:00 pm – 9:00 pm
Venue:  PSDC, 1 Jalan Sultan Azlan Shah, 11900 Bayan Lepas, Penang, Malaysia

Admission is free. Refreshments will be provided.

Network and interact with like-minded engineers and researchers before the seminar begins.

Abstract

Interconnect processes and reliability are reviewed for advanced technology nodes.  First, the structure and properties of low-k materials and barrier layers are described.  Next, integration issues are reviewed including patterning, cleans, metallization, chemical mechanical polishing (CMP), and packaging.   The effect of each of these interconnect processes on reliability will be discussed, including electromigration, stress-induced voiding, time dependent dielectric breakdown, and product reliability

Speaker’s Bio Data

Dr. Gambino received his B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and his Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM’s Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM’s manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology. He has published over 90 technical papers and holds over 100 patents.