“End of CMOS Miniaturization and Technology Development Before and After” by Dr Hiroshi Iwai, Vice Dean and a Distinguished Chair Professor, International College of Semiconductor Technology (ICST), National Chiao Tung University, Taiwan ROC & Professor Emeritus, Tokyo Institute of Technology, Yokohama, Japan. IEEE Fellow.

Date: December 3, 2020 (Thursday)
Time: 3:00pm to 5:00pm
RSVP: https://forms.gle/epECYKZcEggmmXXTA

All are cordially invited to attend. Admission is FREE.

Abstract
Recent smart society has been conducted by the progress of semiconductor technologies, especially by that of CMOS miniaturization, and demand for further high-performance CMOS development is increasing. However, the gate length of MOSFETs is approaching its limit of 10nm caused by the leakage current increase, and no more significant performance increase is expected at the level of a single MOSFET. Still the demand of the society is strong, and thus, the industry is squeezing the performance by increasing the MOSFET density per unit area by decreasing interconnect pitch with EUV and stacking the MOSFETs to vertical directions such as nano-sheets. These efforts are expected to continue for another 10 years depending on the cost and market requirements. In addition, new technology development for semiconductor memory, communication, and power devices are being conducted very aggressively. In any case, the importance of semiconductor device will increase significantly in next 30 years. In this talk, the recent development of CMOS towards its limit is explained and the future electronic device engineering combined with biotechnology for the latter half of 21st century is discussed.

Biodata of Speaker
Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo and worked in the research and development of integrated circuit technology for more than 25 years in Toshiba. He is now a professor of Frontier Collaborative Research Center and Dept. of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Japan. Since joining Toshiba, he has developed several generations of high density static RAM’s, dynamic RAM’s and logic LSI’s including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high speed bipolar transistors. He has authored and coauthored more than 600 journal and conference papers.

He has served on many committees of conferences and editors of journals, as well as a member of many evaluation committee of public organizations. For example, the President of the IEEE EDS, an elected member of the IEEE EDS AdCom, an editor of IEEE EDS Newsletter, a guest editor of IEEE Trans. on Electron Devices, and an editor of the Proceedings of ECS Symp. on ULSI Process Integration. He is now the IEEE Division 1 Director for 2010-11. He serves as a visiting professor for many Chinese and Indian universities.

His awards include Local Commendation for Invention from Japan Institute of Invention and Innovation (1990, 2005), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul Rappaport Award (1994), IEICE ES Electronics Award (1998), IEEE EDS J.J.Ebers Award (2001), and JSAP Award for the best paper (2002), IEEE BCTM Award (2007), Yamazaki-Teiichi Prize (2007), IEEE 2008 EDS Distinguished Service Award (2008), The Commendation for Science and Technology by the Minister of Education, Culture, Science and Technology, Prizes for Science and Technology, Development Category Award (2009).

His current research interests are Nano CMOS and Emerging Technologies: High–k gate insulator, Si Nanowire MOSFETs, plasma doping for ultra-shallow junctions, Ni salicide, RF CMOS modeling, and Ge transisters.

Dr. Iwai is, a fellow of IEEE, a member of Electrochemical Society, a fellow of the Japan Society Applied Physics, and a fellow of the Institute of Electronics, Information and Communication Engineers of Japan.