“2D to 3D MOS Technology Evolution for Circuit Designers” by Alvin Loke, PhD, AMD, USA.  IEEE Distinguished Lecturer.

This tutorial is targeted at engineers, managers, and technical personnel who are involved in circuit design, especially using CMOS.

Date:  December 5, 2012 (Wednesday)
Time:  6:00 pm – 9:00 pm
Venue:  PSDC, Room 1202, 1 Jalan Sultan Azlan Shah, 11900 Bayan Lepas, Penang, Malaysia

Admission is free.  Refreshments will be provided.  Network and interact with like-minded engineers and researchers before the seminar begins.

Abstract

Despite increasing economic and technical challenges to scale CMOS, we continue to witness unprecedented performance with 22-nm fully-depleted tri-gate devices now in production.  This tutorial seminar offers a summary of how CMOS device technology has progressed over the past two decades. We will review MOS device and short-channel fundamentals to motivate how device architectures in production have evolved to incorporate elements such as halos and spacers, mechanical strain engineering, high-K dielectric and metal gate, fully-depleted SOI and finally, fully-depleted tri-gate fins.

Speaker

Alvin Loke received the BASc (Eng. Physics) degree from the University of British Columbia in 1992, and the MSEE and PhDEE degrees from Stanford University in 1994 and 1999, respectively.  His doctoral work focused on copper interconnects with low-K polymer dielectrics. From 1998 to 2001, he worked on CMOS technology integration at HP Labs and then at Chartered Semiconductor Manufacturing as an Agilent assignee. In 2001, he transferred to Colorado where he designed CMOS PLL circuits for embedded SerDes and ASIC core clocking. In 2006, he joined Advanced Micro Devices where he currently designs high-speed links and addresses analog/mixed-signal concerns for next-generation CMOS. Alvin has authored 40 publications and holds 12 US patents. He has served on the CICC technical program committee and as Guest Editor of the Journal of Solid-State Circuits. He is presently the SSCS Webinar Taskforce Chair and a SSCS Distinguished Lecturer.