IEEE CEDA All Japan Joint Chapter/CASS Japan Chapter Joint Seminar
Date/Time: 2015 January 15 (Thu) 15:00-16:40
Location: Tokyo Institute of Technology, Lecture Room S321 @ 2F, South Bldg.3, Ookayama Cumpus
http://www.titech.ac.jp/english/maps/ookayama/ookayama.html
#35. South Bldg. 3
Meeting Agenda:
(1) Lecture 1: 15:00-15:55
Title: Fast Conditional Design Rule Checking for 28nm and Below Technologies Using Prufer Encoding
Speaker: Prof. Yih-Lang Li (National Chiao-Tung University)
Commercial Design Rule Checking (DRC) tools have been commonly used as the promise of high yield for semiconductor manufacturing. As technology node enters 28nm and below technologies, design rules become much more complex due to the occurrence of many conditional design rules.
As compared to traditional design rules, conditional design rules demand variable-rule checking totally depending on the scenarios of neighborhood of the polygon under the test. Although DRC tools can deal with this kind of design rules efficiently but it cannot be used as the embedded engine for routers, layout editors and layout generators. This work firstly discusses a potential technique that can be used as the internal engine for layout tools for on-line checking on conditional design rules as well as traditional design rules. Each design rule is first translated into a layout pattern, and then the layout pattern is converted into a proposed skeleton graph to preserve the topology of the layout pattern. After that, to simplify the test on graph isomorphism, we enhance the Pr?fer encoding method to translate each skeleton graph into an enhanced Pr?fer encoded table such that a test on graph isomorphism is reduced into a table comparison that is just a simple number checking. We have not completed this work but already implemented this method to solve the exact layout matching problem, which is a simplified form of this problem. Experiments show its high efficiency of about average 5.5X performance speedup is obtained as compared to the best exact pattern matching method so far.
(2) Lecture 2: 15:55-16:40
Title: The Coming of Age of Microfluidics: EDA Solutions for Enabling Biochemistry on a Chip”.
Speaker: Prof. Tsung-Yi Ho (National Chiao Tung University)
This talk offers attendees an opportunity to bridge the semiconductor ICs/system industry with the biomedical and pharmaceutical industries. This talk will first describe emerging applications in biology and biochemistry that can benefit from advances in electronic “biochips”. The presenters will next describe technology platforms for accomplishing “biochemistry on a chip”, and introduce the audience to both the droplet-based “digital” microfluidics based on electrowetting actuation and flow-based “continuous” microfluidics based on microvalve technology. Next, the presenters will describe system-level synthesis includes operation scheduling and resource binding algorithms, and physical-level synthesis includes placement and routing optimizations.
In this way, the audience will see how a “biochip compiler” can translate protocol descriptions provided by an end user (e.g., a chemist or a nurse at a doctor’s clinic) to a set of optimized and executable fluidic instructions that will run on the underlying microfluidic platform. The problem of mapping a small number of chip pins to a large number of array electrodes will also be covered. Finally, sensor feedback-based cyberphysical adaptation will be covered.
sponsored by
IEEE CEDA All Japan Joint Chapter
IEEE CASS Japan Chapter
No Admission Charge.
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