M. Shoaran, “Next-Generation Closed-Loop Neural Interfaces: Circuit and AI-driven innovations,” in IEEE Solid-State Circuits Magazine, vol. 15, no. 4, pp. 41-49, Fall 2023, doi: 10.1109/MSSC.2023.3309782.
The paper is available here.
More detail here.
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B. Razavi, “Education of Chip Designers at a Large Scale: A Proposal,” in IEEE Solid-State Circuits Magazine, vol. 16, no. 2, pp. 76-83, Spring 2024, doi: 10.1109/MSSC.2024.3395073.
The IEEE Circuits and Systems Society (CASS) is pleased to announce the second call for the 2024 call for Student Travel Support for travel to CASS non-flagship financially co-sponsored conferences. CASS aims to enable the recipients to present their research work at CASS Financially Co-Sponsored Conferences.
Important Dates:
Submission deadline: 12 August 2024
More detail in the following link:
https://ieee-cas.org/post/news/cass-2024-non-flagship-student-travel-support-round-two
This significant milestone marks three-quarters of a century of advancement of the theory, analysis, design, tools, and implementation of circuits and systems.
The anniversary commemorates CASS’s contributions to theoretical foundations, applications, and architectures, as well as circuits and systems implementation of algorithms for signal and information processing.
More detail can be found here:
https://ieee-cas.org/celebrating-75-years-ieee-circuits-and-systems-society
This talk will cover practical challenges for cryogenic CMOS designs for next generation quantum computing. Starting from system level, it will detail the design considerations for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in 14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital processor that supports waveform generation and phase rotation operations combined with a low power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence times were 75.5μS and 73 μS, respectively, in each case comparable to results achieved using conventional room temperature controls. In further tests with transmons, a qubit-limited error rate of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation per qubit under active control is 23mW.
More detail in: https://ieee-cas.org/presentation/webinar/cass-wide-webinar-xxi-low-power-cryo-cmos-design-quantum-computing
Registration in this link
The IEEE International Symposium on Circuits and Systems (IEEE ISCAS 2025) is the flagship conference of the IEEE Circuits and Systems (CAS) Society and the world’s premiere forum for researchers in the active fields of theory, design and implementation of circuits and systems. This is accomplished through technical conference sessions, poster sessions, live demonstration sessions, and publication of conference papers. ISCAS 2025 will be driven by the theme “Technology Disruption and Society” aiming to emphasize the potential of the CAS Society to find innovative solutions to challenges facing society today.
Unless conditions change substantially over the coming year, ISCAS 2025 will be an in-person event and authors are expected to be onsite to present their papers.
