“Microprocessor Design in the Nanoscale Era” by Stefan Rusu of Intel Corporation, who is also a IEEE Fellow.

Date:  July 29, 2013 (Monday)
Time:  7:00 pm – 9:00 pm
Venue: PSDC, ELC2, 1 Jalan Sultan Azlan Shah, 11900 Bayan Lepas, Penang, Malaysia

Admission is free. Refreshments will be provided.

Network and interact with like-minded engineers and researchers before the seminar begins.

Abstract

Moore’s Law has fueled the worldwide technology revolution for over 40 years and will continue to drive higher feature integration in leading-edge microprocessors with multiple cores and larger on-die caches. This presentation will review the trends and challenges of designing processors and SoC’s in the nanoscale era. CMOS process technology will continue its historical scaling trend, while research activities are focusing on novel devices and manufacturing techniques. Process, voltage and temperature variations are driving a paradigm shift from a deterministic to a probabilistic design methodology. Active and leakage power will remain the main limiters for both server and mobile processors. Several techniques to control switching power and leakage with practical examples from Intel designs will be discussed. Continued improvements in packaging technology enhance the cooling capabilities, while providing better power delivery and higher pin counts.

Speaker

Stefan Rusu received the MSEE degree from the Polytechnic University in Bucharest, Romania. His industry experience includes 21 years with Intel Corp. and 6 years at Sun Microsystems. He is presently a Senior Principal Engineer in Intel’s Microprocessor and Graphics Division leading the technology and special circuits design for the Xeon Processors. Stefan has authored over 90 papers on VLSI circuit technology and holds 35 U.S. patents. He is an IEEE Fellow and a member of the Technical Program Committee for ISSCC, ESSCIRC and A-SSCC conferences. Stefan is an Associate Editor of the IEEE Journal of Solid-State Circuits and an elected member of the SSCS AdCom.