“Designing digital modules for high-speed read-out in cryogenic TPC detectors”

Aseem Gupta, SLAC, Instrument Division, Stanford University

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Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

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6:55 – 7:00 PM Intro 7:00 – 7:50 PM Lecture7:50 – 8:00 PM Q&A/Adjourn

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Abstract:

This work presents the implementation of the digital read-out architecture of a System-On-Chip (SoC) ASIC optimized for Time Projection Chamber (TPC) detectors used in neutrino science. The CRYO ASIC works at cryogenic temperatures and performs signal pre-amplification, waveform digitization and channel multiplexing with minimum number of I/Os. The digital back end is optimized to work with cryogenic liquids (LXe, 160K and LAr, 87K) providing data throughput up to 1 Gbps and can be programmed to maintain signal integrity up to 25m cable length. Implemented in 130nm CMOS process, the back-end architecture consists of a digital multiplexer, a custom 12b/14b encoder, a data serializer, and LVDS (Low-Voltage Differential Signaling) drivers with pre-emphasis enhancing techniques. The simulated output jitter of transmitter is 29.3ps, peak-to-peak (0.15UI) driving a 25m cable at 1Gbps data rate.

Bio:

Aseem Gupta received his M.S degree in Electrical and Computer Engineering from Stony Brook University (SUNY), New York in 2015. He is currently a Staff Electronic Engineer at Stanford Linear Accelerator Center (SLAC) Laboratory, Instrumentation Division, Stanford University. He was also a Staff Research Associate at Brookhaven National Laboratory, NY from 2015-2017, where he worked on development of read-out logic for triggering the digital L0 buffer for ATLAS (A toroidal Large Hadron Collider Apparatus) experiment at CERN, Geneva. He is currently focused on development of a waveform digitizer ASIC operating at cryogenic temperatures for neutrino detection in Time Projection Chamber (TPC) experiments such as Deep Underground Neutrino Experiment (DUNE- 87K) and next Enriched Xenon Observatory (nEXO- 113K). His research interests are in high-speed LVDS driver, cable measurements, integrated circuits, and design of back-end architecture with Digital-on-Top methodology in mostly analog ASICs. He has authored/co-authored in various conference publications. He is an active IEEE member.

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