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Events on May, 2021

“Designing digital modules for high-speed read-out in cryogenic TPC detectors” by Dr. Aseem Gupta

Date: May 27th, 2021

“Designing digital modules for high-speed read-out in cryogenic TPC detectors”

Aseem Gupta, SLAC, Instrument Division, Stanford University

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

PROGRAM:

6:55 – 7:00 PM Intro 7:00 – 7:50 PM Lecture7:50 – 8:00 PM Q&A/Adjourn

Registration Link: Here

Abstract:

This work presents the implementation of the digital read-out architecture of a System-On-Chip (SoC) ASIC optimized for Time Projection Chamber (TPC) detectors used in neutrino science. The CRYO ASIC works at cryogenic temperatures and performs signal pre-amplification, waveform digitization and channel multiplexing with minimum number of I/Os. The digital back end is optimized to work with cryogenic liquids (LXe, 160K and LAr, 87K) providing data throughput up to 1 Gbps and can be programmed to maintain signal integrity up to 25m cable length. Implemented in 130nm CMOS process, the back-end architecture consists of a digital multiplexer, a custom 12b/14b encoder, a data serializer, and LVDS (Low-Voltage Differential Signaling) drivers with pre-emphasis enhancing techniques. The simulated output jitter of transmitter is 29.3ps, peak-to-peak (0.15UI) driving a 25m cable at 1Gbps data rate.

Bio:

Aseem Gupta received his M.S degree in Electrical and Computer Engineering from Stony Brook University (SUNY), New York in 2015. He is currently a Staff Electronic Engineer at Stanford Linear Accelerator Center (SLAC) Laboratory, Instrumentation Division, Stanford University. He was also a Staff Research Associate at Brookhaven National Laboratory, NY from 2015-2017, where he worked on development of read-out logic for triggering the digital L0 buffer for ATLAS (A toroidal Large Hadron Collider Apparatus) experiment at CERN, Geneva. He is currently focused on development of a waveform digitizer ASIC operating at cryogenic temperatures for neutrino detection in Time Projection Chamber (TPC) experiments such as Deep Underground Neutrino Experiment (DUNE- 87K) and next Enriched Xenon Observatory (nEXO- 113K). His research interests are in high-speed LVDS driver, cable measurements, integrated circuits, and design of back-end architecture with Digital-on-Top methodology in mostly analog ASICs. He has authored/co-authored in various conference publications. He is an active IEEE member.

Zoom Broadcast:

Amit Jha is inviting you to a scheduled Zoom meeting.

Topic: Amit Jha’s Zoom Meeting

Time: May 27, 2021 07:00 PM Pacific Time (US and Canada)

Join Zoom Meeting

https://us02web.zoom.us/j/89912834102?pwd=WnV2a0dkWk5QMWtQZWxvQzlYMHZ3UT09

Meeting ID: 899 1283 4102

Passcode: 526734

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Meeting ID: 899 1283 4102

Passcode: 526734

Find your local number: https://us02web.zoom.us/u/kbNy4FSvy1

Admission Fee:

All admissions free. Suggested donations:

Non-IEEE:  $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3


Fault Tolerant Smart Power Drivers with Biasing Schemes and Diagnostics for Smart Automotive Systems

Date: May 13th, 2021

Dr. –Ing Sri Navaneeth Easwaran, Texas Instruments

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

Registration Link: here

PROGRAM:

6:55 – 7:00 PM Intro 7:00 – 7:50 PM Lecture7:50 – 8:00 PM Q&A/Adjourn

Abstract:

The electronic components are increasing in automotive applications replacing earlier mechanical and hydraulics solutions. With proper protection and diagnostics, we can ensure that these electronic components (power semiconductors/transistors) perform the expected function and achieve fail silent (fault tolerant) operation by sensing the fault and adapting its behavior. They also incorporate advanced and robust diagnostic circuits that provideinformation apriori for safety to the drivers/passengers in the cars about the load conditions, faults etc. Such components are referred to as the Smart Power Circuits. Their designs are not much different from the conventional analog circuits used in consumer electronics topology wise. However, they have to handle a wide range of input voltage (5V to 40V) and wide range of currents (30mA to 4A). There are additional system requirements and design implementation challenges that have to be considered when defining and implementing such circuits. This seminar/tutorial introduces the State-of-the-Art requirements of automotive ICs, design techniques, R-L-C type of loads, thermal simulations, reliability and explains the various Gate Drivers like the high side driver, low side driver configurable high side/low side drivers. Power supply sequencing, level shifters, charge pump, voltage-current selector circuits will be presented. High voltage, negative voltage tolerant switches for diagnostics and impact of on chip parasitic bipolar transistors in automotive applications are discussed.

Bio:

Dr. –Ing Sri Navaneeth Easwaran, Senior Member IEEE, received his Bachelor’s (1998, Bharathidasan University), Master’s (2006, University Twente) degrees in Electrical Engineering and Dr. –Ing. degree from University of ErlangenNuremberg in 2017. He worked at SPIC Electronics, STMicroelectronics, Philips Semiconductors between 1998 and 2006. From 2006 he is with Texas Instruments (TI) where he was the design lead for airbag squib driver ICs. He has also designed high voltage and -40V tolerant circuits for automotive ICs. He is an IET Fellow (since Feb 2021) and a TI Senior Member Technical Staff. He has 20+ granted patents and 15 publications. He has offered tutorials on Automotive design at IEEE Conferences.

Zoom Broadcast:

Amit Jha is inviting you to a scheduled Zoom meeting.

Topic: Amit Jha’s Zoom Meeting

Time: May 13, 2021 07:00 PM Pacific Time (US and Canada)

Join Zoom Meeting

https://us02web.zoom.us/j/89090589374?pwd=bG5uT2FuWGc1Q3lOVXJMUUZ2QnJGdz09

Meeting ID: 890 9058 9374

Passcode: 315340

One tap mobile

+12532158782,,89090589374#,,,,*315340# US (Tacoma)

+13462487799,,89090589374#,,,,*315340# US (Houston)

Dial by your location

+1 253 215 8782 US (Tacoma)

+1 346 248 7799 US (Houston)

+1 669 900 6833 US (San Jose)

+1 312 626 6799 US (Chicago)

+1 929 436 2866 US (New York)

+1 301 715 8592 US (Washington DC)

Meeting ID: 890 9058 9374

Passcode: 315340

Find your local number: https://us02web.zoom.us/u/keiRzTDt6Q

Admission Fee:

All admissions free. Suggested donations:

Non-IEEE:  $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3


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