IEEE Transactions on Nanotechnology
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TNANO Article in focus: April 2016

Wednesday, April 13th, 2016

From the March 2016 issue of IEEE Transactions on Nanotechnology

Fabrication and Characterization of Mesoscopic Perovskite Photodiodes

by S. Casaluci, L. Cinà, F. Matteocci, P. Lugli, A. Di Carlo
T-NANO, Vol. 15, Issue 2, pp. 255- 260, March 2016.

 

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Abstract: Mesoscopic photodiodes were fabricated with hybrid organic/inorganic perovskite as absorber layer and Spiro-OMeTAD as hole transport Layer. The perovskite layer was grown using a two-step deposition technique. Our photodiode in addition to a good rectification behavior (three orders of magnitude, range -1 to 1 V) shows a small noise current (< 1 pA/(Hz)1/2), a high responsivity value (0.35 A/W) at 500 nanometers, and a good spectral response in the entire visible range. The Bode analysis shows a bandwidth of 108 KHz.

 

TNANO Article in focus: March 2016

Wednesday, March 30th, 2016

From the March 2016 issue of IEEE Transactions on Nanotechnology

Ultracompact Graphene Multigate Variable Resistor for Neuromorphic Computing

by M. Darwish, V. Calayir, L. Pileggi, J. A. Weldon,
T-NANO, Vol. 15, Issue 2, pp. 318 – 327, March 2016.

 

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Abstract: Brain-inspired or neuromorphic computing has been proposed as a method to overcome the limitations of the von-Neumann architecture. Neuromorphic computing relies on an array of neurons interconnected locally through synapses to perform computing functions such as pattern recognition and image processing. Neuromorphic computing with CMOS-based circuits has limited utility due to the relatively large area required by neurons and synapses, limiting the size of the neuromorphic network implementable on chip. In this paper, we present a novel ultracompact graphene variable resistor that can be used to implement both neurons and synapses. To illustrate the functionality of the proposed devices, we present a 3-bit digitally controlled synapse prototype that occupies 3 um × 9.3 um. The proposed devices pave the way for high-performance large neuromorphic networks that can be integrated with CMOS to augment its functionality or for beyond CMOS computation.

 

TNANO Article in focus: February 2016

Saturday, February 6th, 2016

From the January 2016 issue of IEEE Transactions on Nanotechnology

Computationally Efficient Multiple-Independent-Gate Device Model

by A. Antidormi, S. Frache, M. Graziano, P.-E. Gaillardon, G. Piccinini, G. De Micheli,
T-NANO, Vol. 15, Issue 1, pp. 2 – 14, January 2016.

 

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Abstract: Nanowire field effect transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control, and are regarded as promising candidates for next-generation transistors. Being inherently more complex than the conventional gate-all-around nanowire FETs, they require longer simulation time, especially with numerical simulations. We present a new model, enabling the efficient computation of voltages and current in modular semiconductor structures with an arbitrary number of independent gate regions. Its validity extends on gate-all-around MOSFETs, FinFETs, and gateless channels. It exploits existing models for conventional devices and builds results on top of these. Being completely general, the method is independent from the models used to describe each region, a charge-based model in our case. Applied to a multiindependent-gate nanowire FET structure, extensive comparison of the proposed method with results from physics-based TCAD Atlas software and with numerical exact results show very good agreement with relative errors of less than 1.8% for potentials and less than 4% for currents, under a broad variations of physical parameters as well as biasing conditions. Interpreted language implementation shows a performance advantage in excess of one order of magnitude with respect to standard optimized numerical methods, still providing excellent accuracy, and making it suitable for implementation in circuit simulators.

 

TNANO Article in focus: January 2016

Monday, January 18th, 2016

From the January 2016 issue of IEEE Transactions on Nanotechnology

Novel Nano-Device to Measure Voltage-Driven Membrane Transporter Activity

by Rikiya Watanabe, Naoki Soga, and Hiroyuki Noji T-NANO, Vol. 15, Issue 1, pp. 70 – 73, January 2016.

 

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ALBiC with nano-sized electrode (el-ALBiC). (a) A bright-field image of the through-hole structures on a fabricated nano-device. (b) Schematic illustration of el-ALBiC that displays through-hole structures on a double layer of fluororesin (h = 500 nm) and Au (h = 500 nm). Individual orifices on through-hole structures are sealed with lipid-bilayer membranes.
 

Abstract: The use of an arrayed lipid bilayer chamber system (ALBiC) enables highly sensitive quantitative analysis of membrane transporter activity, a major target of pharmaceutical research. Although membrane voltage is one of the main driving forces of transporters, the versatility of ALBiC is limited to transporter assays in the absence of membrane voltage, owing to technical limitations with voltage modulation. Here, we report a novel nano-device based on ALBiC (el-ALBiC) containing sub-million lipid bilayer chambers, each equipped with nano-sized electrodes. Since the nano-sized electrodes enable quantitative modulation of membrane voltage, the el-ALBiC is capable of performing highly sensitive detection of the voltage-driven membrane transporter activity. Thus, the novel nano-device el-ALBiC extends the versatility of ALBiC and has potential for further analytical and pharmacological applications, such as drug screening.

 

TNANO Article in focus: December 2015

Wednesday, December 2nd, 2015

From the November 2015 issue of IEEE Transactions on Nanotechnology

An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices

by Yuhao Wang; Hao Yu ; Leibin Ni ; Guang-Bin Huang ; Mei Yan ; Chuliang Weng ; Wei Yang ; Junfeng Zhao T-NANO, Vol. 14, Issue 6, pp. 998 – 1012, November 2015.

 

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Abstract: The data-oriented applications have introduced increased demands on memory capacity and bandwidth, which raises the need to rethink the architecture of the current computing platforms. The logic-in-memory architecture is highly promising as future logic-memory integration paradigm for high throughput data-driven applications. From memory technology aspect, as one recently introduced nonvolatile memory device, domain-wall nanowire (or race-track) not only shows potential as future power efficient memory, but also computing capacity by its unique physics of spintronics. This paper explores a novel distributed in-memory computing architecture where most logic functions are executed within the memory, which significantly alleviates the bandwidth congestion issue and improves the energy efficiency. The proposed distributed in-memory computing architecture is purely built by domain-wall nanowire, i.e., both memory and logic are implemented by domain-wall nanowire devices. As a case study, neural network-based image resolution enhancement algorithm, called DW-NN, is examined within the proposed architecture. We show that all operations involved in machine learning on neural network can be mapped to a logic-in-memory architecture by nonvolatile domain-wall nanowire. Domain-wall nanowire-based logic is customized for in machine learning within image data storage. As such, both neural network training and processing can be performed locally within the memory. The experimental results show that the domain-wall memory can reduce 92% leakage power and 16% dynamic power compared to main memory implemented by DRAM; and domain-wall logic can reduce 31% both dynamic and 65% leakage power under the similar performance compared to CMOS transistor-based logic. And system throughput in DW-NN is improved by 11.6x and the energy efficiency is improved by 56x when compared to conventional image processing system.

 

TNANO Article in focus: November 2015

Sunday, November 8th, 2015

From the November 2015 issue of IEEE Transactions on Nanotechnology

A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis Under Process Variation

by Chen, Y.; Sangai, A.; Rogachev, A.; Gholipour, M.; Iannaccone, G.; Fiori, G.; Chen, D.
T-NANO, Vol. 14, Issue 6, pp. 1068 – 1082, November 2015.

 

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Abstract: This paper presents the first parameterized SPICE-compatible compact model of a graphene nano-ribbon field-effect transistor (GNRFET) with doped reservoirs, also known as MOS-type GNRFET. The current and charge models closely match numerical TCAD simulations. In addition, process variation in transistor dimension, line edge roughness, and doping level in the reservoirs are accurately modeled. Our model provides a means to analyze delay and power of graphene-based circuits under process variation, and offers design and fabrication insights for graphene circuits in the future. We show that line edge roughness severely degrades the advantages of GNRFET circuits; however, GNRFET is still a good candidate for low-power applications.

 

TNANO Article in focus: October 2015

Friday, October 9th, 2015

From the September 2015 issue of IEEE Transactions on Nanotechnology

Fault Tolerant Design and Analysis of Carbon Nanotube Circuits Affixed on DNA Origami Tiles

by E. Czeizler, P. Orponen T-NANO, Vol. 14, Issue 5, pp. 871 – 877, September 2015.

 

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Abstract: Due to its programmable nature, DNA nanotechnology is currently one of the most advanced and most reliable self-assembly-based methodologies for constructing molecular-scale structures and devices. This makes DNA nanotechnology a highly promising candidate for generating radically new manufacturing technologies. Our specific interest is in the use of DNA as a template and scaffold for the self-assembly of carbon-nanotube field effect transistor (CNFET) circuits. In this paper, we introduced a novel high-level design framework for self-assembling CNFET circuits. According to this methodology, the elements of the circuits, i.e., CNFETs and the connecting carbon nanotube wires, are affixed on different rectangular DNA scaffolds, called tiles, and self-assemble into the desired circuit. The introduced methodology presents several advantages, both at the design level, and for analyzing the reliability of these systems. We make use of these advantages and introduce a new fault-tolerant architecture for CNFET circuits. Then, we analyze its reliability both by computer simulations and by analytical methods.
 

 

 

 

TNANO Article in focus: September 2015

Friday, September 11th, 2015

From the September 2015 issue of IEEE Transactions on Nanotechnology

Beyond the Electrostatic Gate in a Single-Molecule Transistor

by N.D. Lang and P.M. Solomon

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Abstract: Transistor amplification properties of a three-leg spirofluorene-based molecule are investigated, and the transistor is shown to possess usable current, voltage, and power gain. Current gain is facilitated since the source-drain legs are conjugated, whereas the gate (control) leg is unconjugated and spatially orthogonal, and voltage gain is enhanced by the efficient quantum-mechanical coupling to the gate. Full quantum-mechanical calculations were done for all three electrodes, using the density functional formalism and a plane-wave decomposition of the wave functions.