IEEE Transactions on Nanotechnology
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Archive for 2016

TNANO Article in focus: May 2016

Tuesday, May 10th, 2016

From the May 2016 issue of IEEE Transactions on Nanotechnology

Printable Parallel Arrays of Si Nanowire Schottky-Barrier-FETs With Tunable Polarity for Complementary Logic

by Sebastian Pregl; André Heinzig; Larysa Baraban; Gianaurelio Cuniberti; Thomas Mikolajick; Walter M. Weber T-NANO, Vol. 15, Issue 3, pp. 549 – 556, May 2016.

 

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Abstract: In this paper, we present a novel technology of printable bottom-up grown Si nanowire parallel arrays for low-dissipation power electronics. Parallel aligned layers of monocrystalline Si nanowires can be deposited on arbitrary substrates over large areas by the printing process. The presented transistors consist of parallel arrays of longitudinal NiSi2-Si-NiSi2 nanowire heterostructures, which naturally show ambipolar transistor behavior when a single gate is employed. By a double gate architecture, a reconfigurable transitor component is created, for which unipolar p- or n-type characteristics can be obtained depending on the polarity of the second gate. Transfer and output characteristics of these transistors on a Si/SiO2 substrate with back gate, top gate, and reconfigurable double gate architecture are presented here in detail. Very high on/off-current ratios of over 108 are achieved with very low off-currents. Due to the high number of nanowires incorporated into individual parallel arrays, output currents of 0.5 mA and a high yield of functional transistors of close to 100% at nanowire coated areas are demonstrated.

 

TNANO Article in focus: April 2016

Wednesday, April 13th, 2016

From the March 2016 issue of IEEE Transactions on Nanotechnology

Fabrication and Characterization of Mesoscopic Perovskite Photodiodes

by S. Casaluci, L. Cinà, F. Matteocci, P. Lugli, A. Di Carlo
T-NANO, Vol. 15, Issue 2, pp. 255- 260, March 2016.

 

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Abstract: Mesoscopic photodiodes were fabricated with hybrid organic/inorganic perovskite as absorber layer and Spiro-OMeTAD as hole transport Layer. The perovskite layer was grown using a two-step deposition technique. Our photodiode in addition to a good rectification behavior (three orders of magnitude, range -1 to 1 V) shows a small noise current (< 1 pA/(Hz)1/2), a high responsivity value (0.35 A/W) at 500 nanometers, and a good spectral response in the entire visible range. The Bode analysis shows a bandwidth of 108 KHz.

 

TNANO Article in focus: March 2016

Wednesday, March 30th, 2016

From the March 2016 issue of IEEE Transactions on Nanotechnology

Ultracompact Graphene Multigate Variable Resistor for Neuromorphic Computing

by M. Darwish, V. Calayir, L. Pileggi, J. A. Weldon,
T-NANO, Vol. 15, Issue 2, pp. 318 – 327, March 2016.

 

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Abstract: Brain-inspired or neuromorphic computing has been proposed as a method to overcome the limitations of the von-Neumann architecture. Neuromorphic computing relies on an array of neurons interconnected locally through synapses to perform computing functions such as pattern recognition and image processing. Neuromorphic computing with CMOS-based circuits has limited utility due to the relatively large area required by neurons and synapses, limiting the size of the neuromorphic network implementable on chip. In this paper, we present a novel ultracompact graphene variable resistor that can be used to implement both neurons and synapses. To illustrate the functionality of the proposed devices, we present a 3-bit digitally controlled synapse prototype that occupies 3 um × 9.3 um. The proposed devices pave the way for high-performance large neuromorphic networks that can be integrated with CMOS to augment its functionality or for beyond CMOS computation.

 

TNANO & TETC Joint Special Section

Sunday, February 21st, 2016

Joint Special Section on VLSI and Nanotechnology Design Trends for Computing Innovations

IEEE Transactions on Nanotechnology and IEEE Transactions on Emerging Topics in Computing seek original manuscripts for a Special Section tentatively scheduled to appear in the September 2017 issues. The topics of interest for this special section include:

  • VLSI Design: Design of ASICs, microprocessors/micro-architectures, embedded processors, digital systems, NoC, interconnects, memories, and FPGAs.
  • VLSI Circuits: digital circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits.
  • Low Power and Power Aware Design: Circuits, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools.
  • Computer-Aided Design (CAD): Hardware /software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floor planning, compaction), algorithms and complexity.
  • Testing, Reliability, Fault-Tolerance: Digital testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability, and variation-aware design.
  • Emerging Technologies & Post-CMOS VLSI: Analysis, circuits and architectures, modeling, CAD tools and design methodologies for nanotechnologies, molecular electronics, quantum devices, biologically-inspired computing, spintronic technology, CNT, MTJ, NML, PCM, PMC, and sensor and sensor networks, etc.

Submission Information:

Submitted articles must not have been previously published or currently submitted for journal publication elsewhere. An extended version of an article appearing in a conference proceedings (and in particular, GLSVLSI 2016) can be submitted provided that it has substantially new content w.r.t. to the original conference version. The conference paper must be cited in the main text and the cover letter must clearly describe the differences with the conference version and clearly identify the new contributions. As an author, you are responsible for understanding and adhering to the submission guidelines. Authors are invited to submit manuscripts focused on topics of computing directly to Transactions on Emerging Topics in Computing (TETC) at https://mc.manuscriptcentral.com/tetc-cs and papers focused on topics of nanoscale circuits and technology directly to Transactions on Nanotechnology (TNano) at https://mc.manuscriptcentral.com/tnano. Authors should be aware that papers can be published in TNano or TETC depending on the availability of space with the final allocation at the discretion of the Editor-in-Chief of the respective Transactions. Please address all correspondence regarding this Special Section to the Guest Editors (email: tpc.chairs@gmail.com).

Important Dates:

The following is the tentative timeline for the special issue:

  • Submission Deadline: September 30, 2016
  • Author Notification: December 1, 2016
  • Revised Manuscript Due: February 1, 2017
  • Notification of Acceptance: May 1, 2017
  • Final Manuscript Due: June 1, 2017
  • Tentative Publication Date: September 2017

Guest Editors

Laleh Behjat, University of Calgary,

Ayse Coskun, Boston University

Jie Han, University of Alberta

Martin Margala, University of Massachusetts Lowell

See Call for Papers here.

TNANO Article in focus: February 2016

Saturday, February 6th, 2016

From the January 2016 issue of IEEE Transactions on Nanotechnology

Computationally Efficient Multiple-Independent-Gate Device Model

by A. Antidormi, S. Frache, M. Graziano, P.-E. Gaillardon, G. Piccinini, G. De Micheli,
T-NANO, Vol. 15, Issue 1, pp. 2 – 14, January 2016.

 

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Abstract: Nanowire field effect transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control, and are regarded as promising candidates for next-generation transistors. Being inherently more complex than the conventional gate-all-around nanowire FETs, they require longer simulation time, especially with numerical simulations. We present a new model, enabling the efficient computation of voltages and current in modular semiconductor structures with an arbitrary number of independent gate regions. Its validity extends on gate-all-around MOSFETs, FinFETs, and gateless channels. It exploits existing models for conventional devices and builds results on top of these. Being completely general, the method is independent from the models used to describe each region, a charge-based model in our case. Applied to a multiindependent-gate nanowire FET structure, extensive comparison of the proposed method with results from physics-based TCAD Atlas software and with numerical exact results show very good agreement with relative errors of less than 1.8% for potentials and less than 4% for currents, under a broad variations of physical parameters as well as biasing conditions. Interpreted language implementation shows a performance advantage in excess of one order of magnitude with respect to standard optimized numerical methods, still providing excellent accuracy, and making it suitable for implementation in circuit simulators.

 

TNANO Article in focus: January 2016

Monday, January 18th, 2016

From the January 2016 issue of IEEE Transactions on Nanotechnology

Novel Nano-Device to Measure Voltage-Driven Membrane Transporter Activity

by Rikiya Watanabe, Naoki Soga, and Hiroyuki Noji T-NANO, Vol. 15, Issue 1, pp. 70 – 73, January 2016.

 

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ALBiC with nano-sized electrode (el-ALBiC). (a) A bright-field image of the through-hole structures on a fabricated nano-device. (b) Schematic illustration of el-ALBiC that displays through-hole structures on a double layer of fluororesin (h = 500 nm) and Au (h = 500 nm). Individual orifices on through-hole structures are sealed with lipid-bilayer membranes.
 

Abstract: The use of an arrayed lipid bilayer chamber system (ALBiC) enables highly sensitive quantitative analysis of membrane transporter activity, a major target of pharmaceutical research. Although membrane voltage is one of the main driving forces of transporters, the versatility of ALBiC is limited to transporter assays in the absence of membrane voltage, owing to technical limitations with voltage modulation. Here, we report a novel nano-device based on ALBiC (el-ALBiC) containing sub-million lipid bilayer chambers, each equipped with nano-sized electrodes. Since the nano-sized electrodes enable quantitative modulation of membrane voltage, the el-ALBiC is capable of performing highly sensitive detection of the voltage-driven membrane transporter activity. Thus, the novel nano-device el-ALBiC extends the versatility of ALBiC and has potential for further analytical and pharmacological applications, such as drug screening.