IEEE Transactions on Nanotechnology
IEEE

TNANO Article in focus: February 2016

From the January 2016 issue of IEEE Transactions on Nanotechnology

Computationally Efficient Multiple-Independent-Gate Device Model

by A. Antidormi, S. Frache, M. Graziano, P.-E. Gaillardon, G. Piccinini, G. De Micheli,
T-NANO, Vol. 15, Issue 1, pp. 2 – 14, January 2016.

 

feb2016

Abstract: Nanowire field effect transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control, and are regarded as promising candidates for next-generation transistors. Being inherently more complex than the conventional gate-all-around nanowire FETs, they require longer simulation time, especially with numerical simulations. We present a new model, enabling the efficient computation of voltages and current in modular semiconductor structures with an arbitrary number of independent gate regions. Its validity extends on gate-all-around MOSFETs, FinFETs, and gateless channels. It exploits existing models for conventional devices and builds results on top of these. Being completely general, the method is independent from the models used to describe each region, a charge-based model in our case. Applied to a multiindependent-gate nanowire FET structure, extensive comparison of the proposed method with results from physics-based TCAD Atlas software and with numerical exact results show very good agreement with relative errors of less than 1.8% for potentials and less than 4% for currents, under a broad variations of physical parameters as well as biasing conditions. Interpreted language implementation shows a performance advantage in excess of one order of magnitude with respect to standard optimized numerical methods, still providing excellent accuracy, and making it suitable for implementation in circuit simulators.

 

Comments are closed.