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Si-passivated Ge Gate Stacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

October 22 @ 16:00 - 17:00

Free
Speaker: Laura Zurauskaite, KTH Royal Institute of Technology
Abstract:
Ultra-thin epitaxially grown Si layers have been used for Ge surface passivation in CMOS devices utilizing standard silicon SiO2/HfO2 gate stack. In this work, we propose a high-k TmSiO interfacial layer, which has shown excellent performance on Si, instead of the chemical SiO2. We successfully transfer a TmSiO/Tm2O3/HfO2 gate stack from silicon to Si-passivated Ge devices, yielding interface state density of 3·1011 eV-1cm-2, which is comparable to GeOx passivation. Moreover, Si-capped Ge gates with TmSiO interfacial layer achieve significant improvement in oxide trap density compared to GeOx passivation, exhibiting a potential for superior reliability. We further investigate the robustness of Si layer growth process and show that small (±3 ˚C) variations of growth temperature can be detrimental to the interface state density of the gate stacks.
Bio:
Laura Zurauskaite received the B.Sc. degree (cum laude) in Physics from Vilnius University, Vilnius, Lithuania, in 2014. She received the M.Sc. degree in Nanotechnology from KTH Royal Institute of Technology, Stockholm, Sweden, in 2016, where she is currently pursuing a doctoral degree. She is currently engaged in the research of Ge/high-k MOS interfaces, fabrication of Ge MOSFETs and monolithic 3D integration.

Details

Date:
October 22
Time:
16:00 - 17:00
Cost:
Free

Venue

DIgital (Zoom only)
Kista 16440 Sweden

Organizer

IEEE ED Chapter