IEEE

Thursday, March 10, 2016
6:00 PM: Doors open for refreshments and networking
6:30 PM: Panel presentation

 

Registration Required, donation suggested
Click Here To Register and pre-donate
Bring ticket to meeting

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Venue: KeyPoint Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building on Bowers Ave.

Our Thanks To KeyPoint Credit Union

IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue. Many thanks to Doron Noyman of KeyPoint for his support in making that happen.
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Abstract:
The SF Bay Area has been a hotbed to technology development since the beginning of the 20th century. In this interview panel meeting, you’ll hear how Sigurd and Russell Varian came up with the plans for the klystron at Stanford in the late ’30’s, with critical theoretical contributions from Bill Hansen, physics professor. With a focus on Hansen, we’ll see how the theory and practice of microwave tubes developed locally during and after WW II, resulting in small linear accelerators, and eventually into the 2-mile-long Stanford Linear Accelerator, out behind the campus. The klystron and linear accelerator technology is still in use today around the world, as the prime radiation treatment for cancer.

Dave Leeson is in the final stages of a two-volume book on the life and career of Bill Hansen; he’ll give us ‘inside information’ about those early days, and how this breakthrough happened. Richard Winkler built the first 1-MW klystrons for his Stanford degree thesis, and will discuss their construction in the mid-50’s.  Allen Odian describes how the Stanford Linear Accelerator Center (SLAC) got started, some stories about Panofsky, and “first-beam”.  Burton Richter will tell of the early days of SLAC, and stories of how it was constructed and used. he’ll conclude with some of the physics experiments leading up to his Nobel Prize in 1976.

SLAC was the first of the many IEEE milestones dedicated in the SF Bay area

Join us for an interview of Profs. David Leeson and Burton Richter, as Paul Wesling, IEEE Life Fellow, explores this Silicon Valley technology

Panelists:

Prof. David Leeson, consulting professor of Electrical Engineering at Stanford.
Prof. Leeson is finishing a book on Bill Hansen’s career and contributions.

Richard Winkler, Stanford Engr ’53.
Winkler worked on high-power klystrons at Stanford. He went to Shockley Transistor (became Cleavite) just after Noyce and Moore left, and was the first regular employee at SLAC, designing equipment to test the 50-MW klystrons, did klystrons for first medical uses of linear accelerators.

Dr. Allen Odian, PhD from MIT, Fulbright Scholar, Assoc Prof at Univ of Ill.
Dr. Odian joined SLAC in 1961 and was involved with detectors.

Prof. Burton Richter (tentative), Physical Sciences, Stanford, and Director Emeritus at SLAC
Prof. Richter began post-doc work at Stanford in 1956, becoming a professor in 1967, and designed the Stanford Positron-Electron Accelerating Ring (SPEAR). He succeeded Wolfgang “Pief” Panofsky as director of SLAC in 1984.  He shared the 1976 Nobel Prize in Physics for his work on the particle that has been dubbed J/psi.

Paul Wesling will moderate this meeting.

Time & Date: 6pm-8:30pm, Thursday, Jan 14, 2016

 

Sold Out


Venue: KeyPoint Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building on Bowers Ave.

Our Thanks To KeyPoint Credit Union

IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue. Many thanks to Doron Noyman of KeyPoint for his support in making that happen.
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Abstract:

In 1956 Lockheed moved its new division, Lockheed Missile Systems Division to a 275 acre site next to Moffett Field in Sunnyvale; Lockheed had been selected as the systems manager for the Navy’s Polaris Fleet Ballistic Missile and the developer of the missile itself. Lockheed in Silicon Valley went from zero employees in 1956 to more than 28,000 by 1965, far greater growth than HP or Fairchild – perhaps it should have been “Defense Valley,” but that’s another story. Polaris was the first submarine launched ballistic missile in the US’s triad of nuclear defense systems. Extended thru four production generations (Polaris A1, A2 & A3 and Poseidon C3) it was retired from service in the early 1990s. They were followed by Trident I C4 and today’s Trident II D5.  Polaris/Poseidon and Trident, collectively known as the US Navy fleet ballistic missiles recently celebrated a sixtieth anniversary and  they are generally recognized as one of the most successful military industrial programs.

Join four Lockheed senior leaders from then to get a retrospective on Defense Valley of the 1950s and 1960s and the Polaris/Poseidon program that led to today’s Tridents than make up the most secure leg of the strategic Triad.

VIDEO of Presentation

Panelists:

Dave Montague a forty year Lockheed employee retired in 1996 as the President of the Missile Systems Division and a Corporate Vice President.  He came to Silicon Valley in 1957 as an engineer on the new Polaris program and progressed up the supervisory and management chain in guidance and control, systems engineering, and program management positions on Polaris, Poseidon, Trident 1, to executive management of Tactical and Defense systems and Trident II as well as several compartmented programs. He is a fellow of the AIAA and a member of the National Academy of Engineering.  He graduated from Cornell University in 1956

Cliff Kancler  a forty two year Lockheed employee retired in 2007.  Starting in 1965 in Silicon Valley with work on the first digital flight control computer Cliff was a major contributor in computer architecture development for guidance computers and for tactical and defense interceptor computers.  In addition to being part of our strategic defense systems computers from Cliff’s group are circling the solar system and have helped explore the moon.  He has earned recognition as a LM fellow and has a number of patents, and awards. He graduated Rensselaer Polytechnic Institute (RPI) in 1965.

Roy Dreisbach a thirty seven year Lockheed employee retired in 1997.  Upon graduating Menlo College in 1960 Roy joined Lockheed and held senior administrative assignments in Missile Systems, Research and Development, Advanced System, and Space Systems Divisions spanning programs such as Polaris A1 through Trident II as well as Tactical and Defense Systems.  He is an ex-naval aviator, having flown Lockheed Super Constellation early warning aircraft from 1954 to 1958.

Charlie Barndt is a forty eight year Lockheed Martin active employee. Upon graduating from Cornell University in 1965 Charlie joined General Electric as an engineer on Polaris and Poseidon. In 1967 he joined Lockheed as an engineer on Poseidon and Trident I. He progressed up the supervisory and management chain in missile electronics system and subsystems architecture and design, and was a major contributor on Trident II. Charlie is currently serving a third term as a Lockheed Martin Fellow for which he earned initial recognition in 2009. He is a recipient of the US Navy FBM Exceptional Achievement Award, and the Director of Strategic Systems Programs has recognized his 50 years of service in support of the US Navy FBM Program.

Moderator Tom Gardner from the valley’s storage industry would prefer call it the “Iron Oxide Valley,” but has learned much about Defense Valley preparing for this panel.

Time & Date: To be determined

…………………………………………………………………………
Venue: KeyPoint Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building on Bowers Ave.

Our Thanks To KeyPoint Credit Union

IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue. Many thanks to Doron Noyman of KeyPoint for his support in making that happen.
………………………………………………………………………….

Abstract:
The SF Bay Area has been a hotbed to technology development since the beginning of the 20th century. In this interview panel meeting, you’ll hear how Sigurd and Russell Varian came up with the plans for the klystron at Stanford in the late ’30’s, with critical theoretical contributions from Bill Hansen, physics professor. With a focus on Hansen, we’ll see how the theory and practice of microwave tubes developed locally during and after WW II, resulting in small linear accelerators, and eventually into the 2-mile-long Stanford Linear Accelerator, out behind the campus. The klystron and linear accelerator technology is still in use today around the world, as the prime radiation treatment for cancer.

Dave Leeson is in the final stages of a two-volume book on the life and career of Bill Hansen; he’ll give us ‘inside information’ about those early days, and how this breakthrough happened. Following Dave’s discussions, Dr. Burton Richter will tell of the early days of SLAC, and stories of how it was constructed and used. he’ll conclude with some of the physics experiments leading up to his Nobel Prize in 1976.

Join us for an interview of Profs. David Leeson and Burton Richter, as Paul Wesling, IEEE Life Fellow, explores this Silicon Valley technology

Panelists:

Prof. David Leeson, consulting professor of Electrical Engineering at Stanford.
Prof. Leeson is finishing a book on Bill Hansen’s career and contributions.

Prof. Burton Richter (tentative), Physical Sciences, Stanford, and Director Emeritus at the Stanford Linear Accelerator Center.
Prof. Richter began post-doc work at Stanford in 1956, becoming a professor in 1967, and designed the Stanford Positron-Electron Accelerating Ring (SPEAR). He succeeded Wolfgang “Pief” Panofsky as director of SLAC in 1984.  He shared the 1976 Nobel Prize in Physics for his work on the particle that has been dubbed J/psi.

Paul Wesling will moderate this meeting.

IEEE Consumer Electronics Society (CES) was able to recruit  Joe Decuir –  one of the original designers for the chips used in the Atari 2600 (see bio below) and helped build the video game industry.  His talk will include a historical view of the Atari 2600 which changed the course of video game console design.

Abstract:

Speaker Bio:  

Joe Decuir, IEEE CE Society Distinguished Lecturer & Board Member was a  System Engineer for the Atari 2600 & Atari 800 products.

Joe is still having an interesting career.  He is an IEEE Fellow for contributions to video games and computer graphics (Atari and Amiga).  He has spent a long time since on wired and wireless communications standards, including dial up modems, USB and Bluetooth.  He is still working on the “Internet of Things” (aka “internet of threats”).  Joe is a distinguished lecturer for IEEE Consumer Electronics Society.  He is also on the CES Board of Governor.  He is the chair of the 2015 Global Humanitarian Technology Conference.

Admission Fee: Open to all – to attend

Date & Time-line:

July 28, 2015
6:30 – 7:00 Pizza + Soft Drinks, Networking
7:00 – 8:30 Talk and Questions/Answers

Meeting Place:   

NVIDIA -Marco Polo Room,Building E
2800 Scott Blvd., Santa Clara, CA

Please Register Here    (Please register in advance.  If you cannot register in advance, you can still show up at the door, but seating is not guaranteed.  Please allow extra time for NVIDIA security sign in.)
IEEE CES members – free
IEEE Student members – free
IEEE members – $5 (pay at door)
non-members – $10 (pay at door) You do not need to be an IEEE member to attend!

IEEE CES Upcoming Events are listed here.

Time & Date:  6pm-8:30pm  June 1, 2015
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Venue:   KeyPoint Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building  on Bowers Ave.

Note of Appreciation:  IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue.   Many thanks to Doron Noyman of KeyPoint for his support in making that happen.
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Abstract:

Electronic Design Automation (EDA) for LSI/VLSI Integrated Circuits not only helped meet the challenge of designing systems on a chip (SoC), but also played a crucial enabling role in development of the fabless model that’s so pervasive in today’s semiconductor industry.  EDA allowed system engineers to design chips and gave companies flexibility in targeting an IC design to available semiconductor fabs for manufacturing LSI and VLSI chips.

Companies like Cirrus Logic, Chips & Technologies, and Xilinx were among the first to “truly” separate the design of chips from their manufacturing in the mid 1980’s.  Prior to that time, each semiconductor company had their own silicon waver fabrication plant(s).  Both small and large leading edge semiconductor companies exploit the fabless semiconductor business model today.

This panel will recount the developments in EDA that took place from mid 1970’s to end of 1980’s and share with the audience their insights into how EDA helped transform the semiconductor industry into the fabless semiconductor mode.

Panelists:  

  • Suhas Patil, Cirrus Logic
  • Aart de Geus, Synopsys
  • Doug Fairbairn, VLSI Technology

Panel Moderator:   Alan J Weissberger, Chair-IEEE SV Tech History Committee

Bio’s of Panelists:

1. Suhas S. Patil, ScD EE

Suhas Patil is founder and retired Chairman of Cirrus Logic, Inc. a leading semiconductor company in US. He is co-founder of The Indus Entrepreneurs (TIE) world’s largest nonprofit for fostering entrepreneurs and served as its founding president.

Before becoming an entrepreneur, Dr. Patil was Assistant Professor of Electrical Engineering (EE) at MIT where from 1972 to 1974 he also served as Assistant Director of Project MAC (Multi-Access Computer), where leading edge work was done on time-sharing and on line computer systems.  In 1966 Prof. Patil developed one of the first on line information management systems for the department of Electrical Engineering at MIT.   From 1975 to 1980 Dr. Patil was an Associate Professor of Computer Science at University of Utah where he started the VLSI (very large-scale integrated circuits) group and worked on design methodology for design of complex integrated circuits.

In 1980 Dr. Patil started Patil Systems, Inc. a semiconductor company based on his academic work in design automation of IC. In 1984 this company moved to Silicon Valley from Salt Lake City, Utah and changed its name to Cirrus Logic, Inc. High volume commercial SoC chips for set top units developed at Patil Systems, Inc. in early 1980 showed viability the fabless model of semiconductor industry.

Suhas received the Doctor of Science degree (ScD) in Electrical Engineering from MIT in 1970.  In 1995 Indian Institute of Technology (IIT), Kharagpur conferred Honorary Doctor of Science degree on Suhas for his work in science and industry.  He served on the board of trustee of The Computer History Museum, The Tech and the World Affairs Council of Northern California from. In February, 2003 Dr Patil was named Life Fellow of Indian Institute of Technology, Kharagpur.

2.  Aart de Geus, PhD EE

Aart de Geus is the founder, chairman and CEO of Synopsys Inc. He is a fellow of the IEEE and a Phil Kaufman Award award winner.  Aart received  a PhD in EE from Southern Methodist University, Texas, USA.

Since co-founding Synopsys in 1986, Dr. de Geus has expanded Synopsys from a start-up synthesis company to a global high tech leader. Long considered a pioneer in our industry, he’s been recognized for his technical, business and community achievements with multiple awards, including Electronic Business Magazine’s “CEO of the Year,” the IEEE Robert N. Noyce Medal, the GSA Morris Chang Exemplary Leadership Award, the Silicon Valley Engineering Council Hall of Fame Award, and the SVLG Life-time Achievement Award. He serves on the Boards of the Silicon Valley Leadership Group, Applied Materials, the Global Semiconductor Alliance, and the Electronic Design Automation Consortium.

3.  Doug Fairbairn, MSEE

Doug Fairbairn is Staff Director at the Computer History Museum and also his own photography business – Douglas Fairbairn Photography.   Doug earned a BS/MSEE at Stanford in 1971.  After graduation, Doug joined Xerox PARC as a systems engineer. While at PARC, he teamed up with Carver Mead and Lynn Conway to help develop the Mead Conway VLSI design methodology.

Leveraging that work, he formed VLSI Design Magazine (Lambda at the time) and was a co-founder of VLSI Technology in 1980. At VLSI Doug managed its leading edge IC design tools and ASIC business units.

Doug left VLSI in 1990 to form Redwood Design Automation and was later a division manager at Cadence after its purchase of Redwood in 1994.  Since leaving Cadence in 1998, he has served on the Boards of Catalytic, Quickfilter, Simutech, and Verisity.  He joined CHM and formed his photography business in 2006.

About the Moderator:

Alan J Weissberger, ScD EE was hired by Fairchild Systems Technology in March of 1970 to work on CAD algorithms and software to automate the layout of printed circuit boards.  Fairchild wanted to sell such a tool to its semiconductor customers and use it internally for its Sentry IC Tester and the family of 8, 16, and 32 bit minicomputers (known internally as Sprint) it was developing at that time.  In Sept 1970 the minicomputer division was shut down and Weissberger was laid off without ever working on the CAD project.

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Time-line (for all our meetings held at KeyPoint):

6pm-6:30pm:        Networking and light dinner/non-alcoholic drinks ($5 donation requested)
6:30pm-6:35pm:   Opening Remarks & Introductions
6:35pm-8pm:        Panel Discussion
8pm-8:15pm:        Audience Q & A
8:15pm:                Appreciation & Adjournment; informal chit-chat with panelists
8:30pm:                Everyone must be out of the auditorium
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REGISTRATION REQUIRED:  Click here to register.

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Invitation to ask a question or comment:

If you’d like to submit a question or issue to discuss during the panel, please send email to: alan.weissberger@ieee.org  OR leave a comment in the box below this post.  There will be ~15 minutes for audience Q&A at the end of our panel discussion.

 

Time & Date:  6:30pm-9pm  April 28, 2015

Venue:  

Western Digital, 1710 Automation Parkway, San Jose, CA 95131
Directions and Map 

For questions related to the Western Digital venue, please contact: Gerardo.Bertero@wdc.com

Registration Required
Click Here To Register
Bring ticket to meeting

 

Abstract:

Hard disk drives are all about higher storage capacity and that means higher areal density. Areal density is the product of linear density (density of bits along the tracks) and track density (density of tracks on the disk surface). In this IEEE SV History committee panel session we will examine how hard disk drive track widths have been reduced over over the last 50 years,  while continuing to be the storage behemoths that we still use today.

Over the 50 years of HDD history various ways have been used to try and reduce the track width of the recorded information.  These have included: improved servo technology, creating patterned tracks on the media surface, shingling recorded tracks and general improvements in head and media technology over time.  The panelists will be able to talk about all of these technologies and how they were trying to reduce HDD track width, increase the track density, and provide higher capacity mass storage products.

 

Moderator:  Tom Coughlin, Coughlin Associates (formerly with Seagate Technology, Maxtor, Micropolis, Ampex, Syquest and other companies)
Panelists:
  • Chris Bajorek, formerly at IBM and Komag
  • Dick Oswald, long time consultant
  • Ed Grochowski, formerly at IBM
  • Bruce Gurney, formerly at IBM and HGST

Timeline (this meeting only):

6:30pm  Networking Reception —   Donation Requested for food/drinks

7:00pm  Chair’s Opening Remarks

7:05pm  Introduction of the Topic by Tom Coughlin

7:15pm-8:30pm  Panel Discussion

8:30pm-8:50pm  Audience Q &A

8:50pm-8:55pm  Appreciation and Adjournment

 

Time & Date:  2pm-3pm  April 16, 2015
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Venue:   Santa Clara Convention Center (Ethernet Tech Summit 2015)

Title: Fireside Chat with Internet Pioneer Larry Roberts

Organizer: Alan J. Weissberger, Chair, IEEE Silicon Valley Technology History Committee

Speaker: Larry Roberts, CEO/Co-Founder, TSL Technologies

Interviewer: Geoff Thompson, Principal, GraCaSi

Abstract:

What can we learn from the origins, emergence,and explosion of the now omnipresent Internet?  Join Internet pioneer (and ARPANET creator) Larry Roberts in exploring how the Internet came about, how it reached its present state, and where it is heading in the future.  This interview will cover both historical lessons and future trends.

Larry Roberts, PhD is best known as the leader of the team that created the ARPANET using packet switching techniques.  The ARPANET was later converted into the current Internet, hence making him one of the true founders of the Internet.  He has received many awards, including the National Academy of Engineering’s Charles Stark Draper Prize “for the development of the Internet”, the AFIP Harry Goode Memorial Award, and the IEEE 2000 Internet Award.  He is a member of the National Academy of Engineering and the American Academy of Arts and Sciences.  The founder and CEO of five telecommunications companies, he has developed many leading edge products to advance Internet capability, QoS, and reliability.  He holds 11 patents and has given invited presentations at many conferences worldwide.  He holds a PhD in electrical engineering, an MSEE, and a BSEE from MIT.

About the Interviewer:

Geoff Thompson is currently Principal at GraCaSi, where he serves as an advisor on networking standards development and a technical expert on intellectual property issues.  He has been a voting member of the IEEE 802.3 (Ethernet) committee for over 30 years and also serves as a Member Emeritus of the IEEE 802 Executive Committee.   He chaired the IEEE 802.3 Working Group and was later 1st Vice Chair of the 802 Executive Committee.  A long-time leader in standards development, he was a Distinguished Member, Technical Staff at Nortel Networks and a Consulting Member, Engineering Staff at Xerox.  Geoff has been a major contributor to the IEEE member discussion group, has participated in many ComSocSCV meetings and is the IEEE Silicon Valley Tech History committee officer in charge of LANs and the Internet. He holds a BSEE from Purdue University.

About the Organizer:

Alan J. Weissberger, ScD EE is the Chair of the IEEE Silicon Valley Technology History Committee, Content Manager for the global IEEE Communications Society (ComSoc) Community website, North America Correspondent for the IEEE Global Communications Newsletter, Chair Emeritus of the IEEE Santa Clara Valley (SCV) ComSoc, and an IEEE Senior Life Member.  He is a former Adjunct Professor in the Santa Clara University Electrical Engineering Department and taught 42 graduate courses there. As a volunteer for the Computer History Museum, SIGCIS.org, and ITHistory.org, he writes technical summaries of lectures and exhibits.  Alan is also a contributing author for the Viodi View.

 Note:  This is an OPEN session (free if you register on-line) at the Ethernet Tech Summit 2015.  Register here.

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Postcript:  

This history session went very well with a smooth flow between Geoff and Larry.  The Q & A was also quite good, except for a question about artificial intelligence in the Internet possibly make it think on its own.  Note that software control over the network does NOT imply artificial intelligence or any thinking machines.  It’s the big data/ analytics software in cloud resident computer servers that might be able to predict outcomes based on past behavior.

Glad we could give credit to Larry as the primary creator of the X.25 protocol and his leading role in commercializing Packet Switched Public Data Networks at Telenet (later sold to GTE).  Telenet was way ahead of AT&T, Sprint and other N.A. X.25 PSPDN carriers.  In the mid to late 1970s, his version of the X.25 protocol was accepted by what is now called BT (British Post Office then) and Orange (Transpac then).  It was later enhanced by ANSI X3S37 and CCITT SG XVII WP2 (which I participated in from 1978-1985).

—>X.25 was the only commercial and international public data network from 1976 to 1993 when the Internet went public and took over (see Larry’s comments below)!   Even ISDN used X.25 on both the B and D channels (Basic Rate access) for packet switching.

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Larry’s comments:

Alan,  What can I say? Your summary is very valuable as virtually no-one has realized that the developed world had a more reliable standardized packet service for almost 2 decades before the Internet.  As to the fireside chat, it went great as Geoff fed new questions to me whenever I stopped. It worked very well.

Another thought: The time slot of 1 hour for this fireside chat was a huge difference from a prepared speech and was a serious benefit in enabling us to cover a large amount of material over a long period of time (several decades).

Thanks,

Larry

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Thanks also to Paul Wesling for being the cameraman/videographer.  He and Ken Pyle will work to get the videos edited and captioned (with the help of Larry & Geoff for the latter).

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 alan.weissberger@ieee.org

 

 

Time & Date:  6pm-8:30pm  April 1, 2015
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Venue:   Key Point Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building  on Bowers Ave.
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Panelists and their company/university affiliations from 1959 (or later)-1975:

  • Bernie Marren: Fairchild, Western Micro Technology, AMI, etc
  • Ted Hoff, Jr:  Stanford University (Researcher), Intel
  • Ed Pausa, Fairchild, National Semiconductor
  • David Laws:  Fairchild,  Litronix (LEDs), AMD

Moderator:  Alan J. Weissberger [Chair of IEEE SV Tech History Committee]:  Fairchild Systems Technology,  National Semiconductor, Signetics (9/76-to-9/79)
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Abstract:

What was the semiconductor industry like in greater Santa Clara County- “the Valley of Hearts Delight”- before the term “Silicon Valley” was coined?   Most of us know that it was Fairchild Semiconductor that started the activity after it’s founders left Shockley Semiconductor Laboratory.

We start our semiconductor journey in 1957,when the “traitorous eight” left Shockley Labs to start Fairchild Semiconductor. How did that happen and what was Bob Noyce’s role? What other semiconductor companies existed in Santa Clara Valley in the late ’50s and what became of them?

In 1959, the integrated circuit (IC) was co-invented separately by Bob Noyce (Fairchild) and Jack Kilby (TI).  What types of discrete components were being sold here from 1957-1962, before the IC was commercially available?  What were their applications (e.g. UHF tuners for TVs)?   Our panelists will address that issue and the general state of the electronics/semiconductor industry before the IC was commercially available (1961-1962).

Did you know that the guy who was hired by Bob Noyce at Fairchild to train engineers on a secret product (the IC) wasn’t even told what it was until it became commercially available two years later?  Bernie Marren will tell that intriguing story, which will be followed by many others.  The panel will address three distinct time periods:

  • 1957-1962   Discrete component (pre-IC) era: transistors, diodes, etc
  • 1962-1968   IC era: digital logic, SSI & MSI, logic families converge to TTL, etc
  • 1968-1975   LSI era:  memories/shift registers, custom LSI, LED displays, consumer electronics, microprocessor applications

Our seasoned semiconductor industry veterans will tell what it was like to work at various Silicon Valley semiconductor companies in the early to mid 1970’s (AMI, National Semiconductor, AMD, Litronix, Intel, etc).  They will share stories about some of the all time great semiconductor icons- like Bob Noyce, Gordon Moore, Charlie Spork, Jerry Sanders, Bob Widlar, Pierre Lamond, and others.

About the Panelists:

Bernie Marren was working on fuses for the Polaris missile at AVCO, before Bob Noyce hired him to work at Fairchild Semiconductor in 1960 to train sales engineers on a secret, undisclosed product (it’s a terrific story).  From 1972 to 1976, Bernie served as the President and Chief Executive Officer of American Microsystems, Inc. (AMI).  He founded and was the first President of SIA. and Western Microtechnology Inc.  (President and CEO from 1977 to 1994).

Marcian “Ted” Hoff, Jr. will describe the semiconductor and electronics courses he took as a PhD student at Stanford along with the electronics design contract work he did as a Post Doc from 1962-1968 before he joined Intel as employee #12.   He will also review selected semiconductor companies that were doing business here and provide an Intel competitors perspective on many of them. Finally, Ted will set the record straight on the main applications of microprocessors from 1971-1975 (and for years later).

Ed Pausa will recount the early days at both Fairchild and National Semiconductor where he rose to be Vice President International Manufacturing and Services from 1973-1990.   During his 45 years in the semiconductor industry Ed directed 33 plants and subsidiary companies in 18 foreign countries  and 11 plants in six US states.

David Laws began his Silicon Valley career at Fairchild in Mountain View in 1968. He later served at LED pioneer Litronix, at Advanced Micro Devices (AMD) for 12 years where his last role was Vice President Business development, and at Altera where he was Vice President of Marketing.  He is currently Semiconductor Curator at the Computer History Museum.  David will provide an insiders view of Advanced Micro Devices (AMD) and its larger than life founder- Jerry Sanders.  He will also engage in dialog with the other panelists about Fairchild’s role in creating so many semiconductor companies in Silicon Valley.

Note that three of our four panelists and the moderator all worked at Fairchild at some point in time.

About the Moderator:

From 1968 to early 1970, moderator Alan J Weissberger worked on real time, minicomputer controlled testing of ICs made by Raytheon Semiconductor in Mt View, CA.  He was co-responsible for a CPU design at Fairchild Systems Technology in 1970 and later worked as a full time employee of National Semiconductor (1973-1976) and Signetics (1976-1979) in the microprocessor/COPs division of those companies.  Alan is the founder and chairman of the IEEE Silicon Valley Tech History committee and a four decade + volunteer for IEEE.

References:

The Rise of Silicon Valley: From Shockley Labs to Fairchild Semiconductor

Who Coined the Term Silicon Valley?

Interview with Bernie Marren by Rob Walker

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Time-line (for all our meetings):

6pm-6:30pm:   Networking and light dinner/non-alcoholic drinks ($5 donation requested)
6:30pm-6:35pm:  Opening Remarks & Introductions
6:35pm-8pm:  Panel Discussion
8pm-8:15pm:  Audience Q & A
8:15pm:  Appreciation & Adjournment; informal chit-chat with panelists
8:30pm:  Everyone must be out of the auditorium
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REGISTRATION REQUIRED: Click here to register

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Invitation to ask a question or comment: If you’d like to submit a question or issue to discuss during the panel, please send email to: alan.weissberger@ieee.org  OR leave a comment in the box below this post.  There will be ~15 minutes for audience Q&A at the end of our panel discussion.

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Comments from David Laws:

  • We don’t know when the term “Silicon Valley” was “coined.” It appeared in print for the first time (as far as we know) on January 11, 1971 Electronic News article written by Don Heffler.
  • Silicon activity in the Valley began not at Fairchild in 1959 but at Shockley Semiconductor Laboratory, 391 San Antonio Road early in 1956.  [Note that this panel session doesn’t cover that earlier time period]
  • Many people built “integrated circuits” before Kilby and Noyce. They include Hawick (RCA 1953), Dill (IBM 1954), D’Asaro (Bell 1954), and Wallmark (RCA 1957). Kilby’s contribution (1958) was to show that it made sense to build resistors out of semiconductor material. Noyce described the concept of using Jean Hoerni’s planar process to build and manufacture an IC in January 1959 and Jay Last’s team built the first working unit on May 11, 1960.

SSI Commercial* Digital Logic Families with Commercial Introduction Dates:

  • Fairchild Micrologic (DCTL) – March 1961
  • TI Series 51 (DCTL) – October 1961
  • Ferranti Micro-NOR (DTL) – 1962
  • Motorola MECL 1 (ECL) – 1962
  • Signetics SE100 (DTL) – 1962
  • Fairchild 900 Series (RTL) – 1963
  • Sylvania SUHL (TTL) – 1963
  • Westinghouse 200 Series (DTL) – 1963
  • Fairchild 930 Series (DTL) – 1964
  • TI Series 53 (DTL) – 1964
  • TI Series 54 (TTL) – 1964
  • Sylvania SUHL II (TTL) – 1965
  • TI Series 70 (ECL) – 1965 (?)
  • Fairchild (CTL) – 1966
  • Motorola MECL II (ECL) – 1966
  • TI Series 74 (TTL) – 1966
  • Motorola MECL III (ECL) – 1968
  • RCA CD4000 (CMOS) – 1968
  • Motorola 10K (ECL) – 1971
  • TI Series 74S (Schottky TTL) – 1971
  • Fairchild 100K (ECL) – 1973 (?)
  • TI Series 74LS (Low-power Schottky TTL) – 1974 (?)
  • Fairchild 74F (Isoplanar TTL) – 1978

* Numerous custom SSI logic families (CML, DTL, ECL, TTL) were developed by mainframe computer manufacturers, including CDC, Honeywell, IBM, NCR, RCA, SDS, and Univac.

Sources:

http://www.vintchip.com/FLATPACK/TEXASINSTRUMENTS.html

http://www.computerhistory.org/semiconductor/timeline/1965-Custom.html

http://www.computerhistory.org/semiconductor/timeline/1963-TTL.html

http://www.computerhistory.org/semiconductor/timeline/1962-Apollo.html

http://www.computerhistory.org/semiconductor/timeline/1963-CMOS.html

http://www.computerhistory.org/semiconductor/timeline/1969-Schottky.html

http://en.wikipedia.org/wiki/Emitter-coupled_logic

http://en.wikipedia.org/wiki/7400_series

http://www.shmj.or.jp/english/integredcircuits/ic60s.html

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Comments from Ted Hoff, PhD:

1. Patent filings:

  • Kilby filed 2/8/1959–issued 6/23/1964
  • Hoerni filed 5/1/1959–issued 3/20/1962
  • Noyce filed 7/30/1959–issued 4/25/1961

2. Importance of planar transistor (Hoerni):

The planar transistor laid the foundation for the integrated circuit, but also the methods used to create the transistors led to gradients of impurities within critical areas of the transistor.  Those gradients tended to speed up the movement of the holes and electrons which in turn made faster devices–with many more applications.

3.  Experience designing with transistors and  integrated circuits (ICs):

At Stanford, we used quite a few 2N706 transistors in logic circuits—in bread boarding ways to realizing adaptive systems, and forinterfacing to our computers.  We had a bank of filters for processing speech and a TV camera for computer input. We also used germanium transistors for some computer interface circuits.

I didn’t really begin to use ICs until after joining Intel in 1968.  Prices were falling and performance improving.  TTL seemed to be the best choice based on ease of use, noise margins, etc.  With the availability of MSI, seemingly more available in TTL than other families, TTL really became the prefered way to make digital logic systems–at least until the microprocessor became available in late 1971.

4.  Semiconductor Memory competitors for Intel:

AMS was founded about the same time as Intel (July 1968), also to develop semiconductor memory.  Back East there was Cogar.  Some of the earliest competition seemed to be from MOSTEK in Dallas, Texas.

5.  History & Importance of Semiconductor Memories:

There was work going on in smaller memory chips, such as bipolar RAMs used to implement arrays of registers in a computer CPU.  Intel had a design specification from Honeywell that led to our 3101–a 16×4 SRAM.  In traveling with Intel sales and marketing people, I often heard customers express appreciation for the support that Intel provided–even if they did not think our IC memory chip was the best, they used it because they felt we would be there to help if they ran into a problem.

Shift registers were another area of interest.  Some companies required customers for shift registers to buy their logic circuits, e.g. TTL, from them to get shift register deliveries.  Intel, was not providing TTL, but got quite a lot of business in shift registers.

6.  Semiconductor memories driving Moore’s Law:

Memories were seen as a driving force in the implementation of Moore’s law, because their large production volumes helped debug the underlying semiconductor production processes, thus improving yields and implementing Gordon Moore’s projections.

7.  Intel Memory Systems:

Intel began its own memory systems development activity, building big box systems to be used with mainframe computers.

8.  Importance of static RAMs for microprocessor applications:

Once the microprocessor gained market traction, the static RAM products became more important than DRAMs.  Quite a few of the earlier computer hobbyist products made use of static RAMs, because they avoided the refresh circuitry (CAS, RAS, etc) needed when using DRAMs

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The  IEEE Milestone Award event recognizing the technological achievement of the SPARC RISC Architecture will be presented at 10am on Feb 13, 2015 at the Oracle Auditorium in Santa Clara, CA.   That’s one day after the UC Berkeley RISC Project milestone is presented as described in the previous post.   The plaque unveiling will be preceded by a dedication ceremony in the Oracle Auditorium beginning at 10:00 am with Bill Joy, Dave Patterson, Andy Bechtolsheim, all instrumental in the early success of the SPARC architecture, listed as planned speakers. IEEE President Howard Michel will also say a few words.  Over 200 IT professionals from throughout the Silicon Valley and beyond are expected to attend.

The Relevance of the SPARC Processor Architecture:

Sun Microsystems introduced SPARC (Scalable Processor Architecture) RISC (Reduced Instruction-Set Computing) in 1987. Building upon UC Berkeley RISC and Sun compiler and operating system developments, SPARC architecture was highly adaptable to evolving semiconductor, software, and system technology and user needs. Over the course of its life the SPARC processor architecture has powered millions of servers and workstations and is still a leading and highly valued technology. Today, Oracle continues to engineer new levels of excellence into the SPARC architecture delivering the highest performance scalable servers, for engineering, enterprise, Internet and cloud computing applications

The first SPARC processor debuted in 1986 and was the CPU for the Sun-4 workstation the following year. In 1992 Sun launched its first high-end SPARC server, the successful SPARCcenter 2000. Today, the SPARC processor family is used in Oracle’s enterprise servers to create architectures that are optimized for a powerful mix of application types, from CRM systems and Java/Web middleware infrastructure applications to mission-critical ERP and back-end OLTP/data warehousing enterprise applications that depend on high availability and scalability.

According to Wikipedia,  there have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit “extended precision” floating-point arithmetic to 128-bit “quad-precision” arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.  SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl CorporationFujitsuICLLSI LogicMatsushitaPhilipsRoss TechnologySun Microsystems, and Texas Instruments.

A very interesting post titled SPARC History from 1987 to 2010 provides more history and background information.

You can register for the Feb 13th event here.

The UC-Berkeley RISC milestone plaque will be unveiled at 3:30 PM Feb. 12, 2015 in the lobby on the 3rd floor of Soda Hall, Berkeley’s Computer Science building. Speakers will include IEEE 2015 President Howard Michel, Professor David Patterson, and several others.

The unveiling will be part of the program for UC-Berkeley’s annual one-day research program (BEARS) that is focused on current research.  Approximately 250 professionals from Silicon Valley and elsewhere will attend. Many of those attendees likely will attend the brief unveiling ceremony and thereby fill the space in the lobby where the plaque will be displayed.

Relevance of the RISC research project:

UC-Berkeley students designed and built the first VLSI reduced instruction-set computer in 1981. The simplified instructions of RISC-I reduced the hardware for instruction decode and control, which enabled a flat 32-bit address space, a large set of registers, and pipelined execution. A good match to C programs and the Unix operating system, RISC-I influenced instruction sets widely used today, including those for game consoles, smartphones and tablets.

From Prof. David Hodges:

In the 1970s, the general trend in in computer design was to increase the complexity of computer architectures. The thought was that this would best exploit the rapidly advancing capabilities of semiconductor technology. The popular DEC VAX 11-780 was the leading example. About 280 machine-language instructions were implemented in the VAX hardware.  The VAX 11-780, a so-called super minicomputer, was advertised as exercising 1 million instructions/second and sold for about $100,000. This class of computers was then termed CISCs, or complex instruction set computers.

UC-Berkeley Professors David Patterson and Carlo Sequin observed that compilers for high-level computer languages, such as C, rarely utilized the added instructions. They thought that overall performance could be improved by optimizing the combination of processor function and memory on a single chip. Better overall performance at a much lower cost might be achieved by simplifying the processor, thereby allowing more chip area to be devoted to memory. Thus the goal was defined as a RISC, or reduced instruction set computer.

The RISC-I project was initiated in 1980 with assignments in a sequence of graduate classes at UC-Berkeley, aiming to validate the RISC hypothesis. Initial conclusions based on simulation were positive, so the project continued, with critical grant support from DARPA. Students designed a processor with just 31 instructions, each executed in a single clock cycle.  Included on the same student-designed chip, were 78 32-bit registers. This was enough memory to enable one-cycle execution of a large fraction of the instructions in compiled code.

Early in the project, the Berkeley team learned of previously unpublished work at IBM around 1975, led by Dr. John Cocke. The IBM 801, never commercialized, pioneered
architectural principles similar to those independently chosen by the Berkeley team, though the goals for the 801 were quite different. Dr. Cocke visited Berkeley in 1981 and spoke to the student-faculty team. He gave them enthusiastic encouragement for their undertaking.  The first student-designed RISC-I chips, realized via the DARPA and NSF-funded MOSIS implementation service, were received in the fall of 1981. They were functional, though with minor deficiencies. However, performance was sufficient to convince previous skeptics to recognize the merits of the RISC approach to design of very large scale integrated (VLSI) computing. After correction of minor design bugs, the RISC-I design proved to outperform the VAX on almost every real-world benchmark.

The biggest obstacle in 1980 was skepticism among knowledgeable professionals, friendly or otherwise. No one on the team had prior experience designing VLSI computer processor chips. Professors Patterson and Sequin had the courage to continue. Of course, the work would not have been possible without the major support of DARPA and MOSIS.   A related MIPS project, led by Prof. John Hennessey at Stanford, featured important attention to the role of the compiler in making best use of RISC processor resources. The first working chip resulting from that project came about a year after RISC-I at Berkeley.

The RISC design was first commercialized as the SPARC microprocessor, introduced in 1987.   Professor Patterson served as a consultant to Sun Microsystems, assisting Sun in

development of the powerful RISC-based SPARC workstations. The SPARC workstations became a leading tool in the design of integrated circuits. Sun Micro is now a part of the Oracle Corporation and will be receiving their own IEEE Milestone for SPARC on February 13, 2015.   A companion post will describe that event, the RISC roots of SPARC, and why it was significant.

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Separately, Advanced RISC Machines (ARM) in the UK developed a continuing series of VLSI RISC processor designs that now are produced under license by leading
semiconductor manufacturers of chips for use in game consoles, smart phones, and tablet computers.

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References:

1.  Patterson, David A., and David R. Ditzel, “The case for the reduced instruction set computer.” ACM SIGARCH Computer Architecture News 8.6 (1980): 25-33.

2. Patterson, David A., and Carlo H. Sequin, “RISC I: A reduced instruction set VLSI computer.” Proceedings of the 8th annual symposium on Computer Architecture, IEEE
Computer Society Press, 1981. Patterson, David A., and Carlo H. Sequin, “Design and Implementation of RISC I” UC Berkeley EECS Technical Report CSD-82-106, 1982. (Also appeared in Proc. Advanced Course on VLSI Architecture, University of Bristol, England, July 19-30, 1982.)

3.  Patterson, David A., and Carlo H. Sequin, “A VLSI RISC.” IEEE computer 15.9 (1982): 8-21.  Digital Object Identifier: 10.1109/MC.1982.1654133

4. Sherburne, R. W., Katevenis, M. G., Patterson, D. A., & Sequin, C. H. (1984), “A 32-bit NMOS microprocessor with a large register file,” Solid-State Circuits, IEEE Journal of,19(5), 682-689. Digital Object Identifier: 10.1109/JSSC.1984.1052208

5.  Patterson, David A. “Reduced instruction set computers.” Communications of the ACM 28.1 (1985): 8-21.

Panel Session on RISC vs CISC in Silicon Valley Race for Microprocessor Leadershiphttp://ithistory.org/blog/?p=1826