Executive Committee

Chairman

Andrew Tay; SUTD

Prof Andrew Tay is an Adjunct Professor at the Singapore University of Technology and Design; Adjunct Professor (formerly Professor of Mechanical Engineering) at the National University of Singapore; a Distinguished Visiting Professor at the Central South University, Changsha, China; and a Visiting Professor at Budapest University of Technology and Economics, Hungary. He is also a free-lance consultant having been engaged as a consultant to more than 40 companies and organizations to date.

Prof Tay obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include electronics packaging (thermo-mechanical failures, delamination, effects of moisture, solder joint reliability, TSVs, 3D ICs); thermal management of electronic systems and EV batteries; thermoreflectance thermography; solar photovoltaics and fracture mechanics. To date Prof Tay has published more than 300 technical papers, 11 keynote presentations at international conferences, 11 invited lectures, 3 panel discussions, written 3 book chapters and co-edited 4 conference proceedings and two special issues of technical journals.

Prof Tay is currently a member of the Board of Governors of the IEEE CPMT Society, a member of the Executive Committee of the Singapore Reliability/CPMT/ED Chapter, and Chairman of the EPTC Board. He was the inaugural General Chair of the 1st Electronics Packaging Technology Conference (EPTC) in 1997, which has now been established as the flagship conference of the IEEE CPMT Society in the Asia-Pacific Region. He has served and is still serving in the International Advisory Boards and Organising committees of several regular international electronics packaging conferences such as DTIP, ECTC, EMAP, EPTC, EuroSime, HDP, ICEPT, IEMT, IMPACT, InterPack, ITHERM and THERMINIC, listed in alphabetical order.

For his exceptional technical achievements, he was awarded the 2012 IEEE CPMT Exceptional Technical Achievement Award, and for his contributions to IEEE CPMT Society Region 10, the 2012 IEEE CPMT Regional Contributions Award. For his outstanding contributions in the application of engineering mechanics to electronics and/or photonics packaging, he was awarded the ASME EPPD Engineering Mechanics Award in 2004. He was also awarded an IEEE Third Millennium Medal in 2000.

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Vice Chairman

Lim Yeow Kheng; STATS ChipPAC

Yeow-Kheng Lim received Bachelor (Hons.), Master and Ph.D. degrees in Electrical and Electronic Engineering from Nanyang Technological University, Singapore in 1999, 2001 and 2008 respectively. He is currently employed as the Deputy Director in embedded Wafer Level BGA (eWLB) of STATS ChipPAC Ltd., Singapore. He has more than 15 years of experience in semiconductor foundries technology development and outsourced semiconductor assembly & test manufacturing and business operations.

Yeow-Kheng is a senior member of IEEE and had published more than 41 international journal/conference papers and 26 patents. Also, he is actively involved in international technical activities such as the Chairman (2012-2013) and Treasurer (2010-2011, 2017) of IEEE Singapore Reliability/ Components, Packaging and Manufacturing Technology/ Electron Devices Chapter; Board Member (2015-2017), General Chair (2014), Technical Chair (2012-2013) and Technical Co-chair (2010-2011) of International Symposium on the Physics & Failure Analysis of Integrated Circuits; Treasurer (2015) of Conference on Electron Devices and Solid-State Circuits; Committee Member (2014-2017) of International Interconnect Technology Conference Advanced Metallisation Conference Asian Program; Technical Sub-committee Member (2009-2017) of International Reliability Physics Symposium; and Committee Member (2014-2017) of Singapore National Working Group for Semiconductor Devices.

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Secretary

Zhang Xiaowu; IME

Dr. Xiaowu Zhang (SM’ 2010) received his Ph.D. degree in Mechanical Engineering from Hong Kong University of Science and Technology (HKUST), Hong Kong, in 1999. Currently, he is a Principal Investigator at the Interconnection & Packaging Program, Institute of Microelectronics (IME), A*STAR, Singapore. He has authored or co-authored more than 200 technical papers in refereed journals and conference proceedings. He holds 11 patents too. One of his patents has been licensed to a MNC two times.

Due to his performance and achievements in electronic packaging research, Dr. Zhang was awarded: (1) the 2015 IEEE CPMT Exceptional Technical Achievement Award (the highest award honouring technical achievement in CPMT Society fields of interest), (2) the 2013 Best Paper Award of IEEE Transactions on CPMT, (3) the 2010 Best Paper Award of IEEE Transactions on CPT, (4) the IEEE EPTC2009 Outstanding Paper Award, (5) the 2001 JEP Best Paper Award of ASME Transaction: Journal of Electronic Packaging.

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Treasurer

Tan Kok Tong, Dave; T2 Integrated Solution

Dave Tan has a career spanning more than 30 years in Engineering, from semiconductor to electrical/electronic and design. He worked in Wafer Fabrication and Assembly fields in the areas of Reliability and Failure Analysis. He is now working in Conceptual Design and Systems Integration for data acquisition, control and monitoring across all industries.

Dave Tan is currently the General Manager in T2 Integrated Solution since 2010. Before joining T2 Integrated Solutions, he was the Assistant General Manager in CentiForce Instruments from 2008-2010, Senior Manager in Systems on Silicon Manufacturing from 2000-2008 and Staff Engineer in National Semicondutor from 1992-2000. He received his Bachelor Degree in Electrical and Electronics Engineering in 1992 from National University of Singapore. He is actively involved in the Singapore IEEE Rel/CPMT/ED Chapter and currently the chairman since 2016.

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Committee Member

Gan Chee Lip; NTU

Dr Gan is a Professor at the School of Materials Science and Engineering, Nanyang Technological University. He is also currently the Director of Temasek Laboratories@NTU and Director of Renaissance Engineering Programme (REP), as well as a Fellow of NTU Teaching Excellence Academy. He had previously held the position of Assistant Chair of Alumni (2006-08) and Head of Materials Science Division (2010-12) in MSE, as well as Chairman of NTU Teaching Council (2012-2014). He was also a Visiting Scientist at Massachusetts Institute of Technology (2008-10), a Singapore-MIT Alliance (SMA) Fellow (2006-2010), and a Faculty Associate at the Institute of Microelectronics (2007-2011). Dr Gan was awarded the National Day Award Bronze Medal (Administration) in 2012.

Dr Gan received his B.Eng (Electrical) from the National University of Singapore in 1999, and Ph.D in Advanced Materials for Micro- and Nano-Systems under the Singapore-MIT Alliance Program (SMA) in 2003. His current research interests include the reliability study of advanced interconnect systems including 3D interconnects, and advanced packaging technology for harsh environment electronics. A related topic is using copper nanostructures for bonding for low temperature bonding. Another research area is on developing shape memory ceramics for defense applications. He has received a number of best paper and poster awards at international conferences, as well as being an invited speaker at these conferences.

Outside of NTU, Dr Gan is a board member of TL@NUS and TL@SUTD. He is also a member of the advisory panel for Republic Polytechnic School of Applied Science. He is a Senior Member of IEEE and past General Chair of International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2010, Technical Chair of IPFA 2008, and currently a IPFA Board member. Dr Gan is also the Vice-Chairman of Woodlands Park Neighbour Committee, having previously served as the Chairman, Treasurer and Assistant Secretary.

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Committee Member

Zhou Xing; NTU

Prof Zhou Xing has been with the School of Electrical and Electronic Engineering since he joined NTU in 1992. He obtained his BEng degree in electrical engineering from Tsinghua University in 1983, MS and PhD degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively. His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development. His recent research focuses on nanoscale CMOS compact model development. His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs.

He has given more than 140 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions. He has been invited for visiting several universities, including Stanford University (1997 and 2001), Hiroshima University (2003), Universiti Teknologi Malaysia (2007), Fudan University (2011), and Tokyo Institute of Technology (2011 and 2012). He is the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference since 2002.

Dr. Zhou was an elected member-at-large of the IEEE EDS Administrative Committee (AdCom/BoG) in 2004–2009 and 2011–2016, EDS vice-president for Regions/Chapters in 2013–2015, chair of the EDS Asia Pacific Subcommittee for Regions/Chapters in 2007–2012, and a member of the EDS Compact Modeling, Membership, Publications, and Educational Activities committees. He was a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices and an editor for the IEEE Electron Device Letters in 2007–2016. He is a member of the modeling & mimulation subcommittee for IEDM (2016, 2017). He has been a senior member of IEEE since 1999 and an EDS distinguished lecturer since 2000,.

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Committee Member

John Thong; NUS

John Thong graduated with a B.A. (1* Hons.) in Electrical Sciences from Cambridge University in 1985, and a PhD in Electrical Engineering from the same university in 1989. In the same year, he was elected to a research fellowship at King’s College, Cambridge, where he remained until 1991.

He joined the Department of Electrical Engineering at NUS as a lecturer in 1992, as was promoted to senior lecturer (1995), associate professor (1999) and professor (2014). He served as sub-dean (Academic) in the Faculty of Engineering Dean’s office from 1998-2000, and deputy group head (1998-2007) and group head (2008-2009) for the microelectronics group. He was served as ECE Deputy Head for research & graduate programs from 2010-14, before his current appointment as Head of Department.

He has held appointments as senior academic associate at IMRE (1998-2000), and is currently an NGS faculty member (since 2003). He has served on various grant review panels for A*STAR SERC and the Ministry of Education. He is actively involved with the IEEE Rel/CPMT/ED Chapter, Singapore Section, as an ex-co member, and with the IEEE International Symposium on the Physical & Failure Analysis of ICs (IPFA) serving on its organization committees as well as the IPFA Board.

Following his PhD research, John’s early research interests were in scanning electron microscopy and related techniques, electron-optical instruments and electron sources. His interests turned to nanotechnology in the early 2000’s, and his research group currently works on various aspects of nanomaterial synthesis, nanostructures and devices, focusing in particular on structural, electrical and thermal properties.

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Committee Member

Chin Jiann Min; AMD

Jiann Min Chin is the Device Analysis Lab Senior Manager at AMD.He leads world-wide AMD DA/FA labs in Austin, Texas and Singapore His main activity includes providing leadership for lab operations supporting the Asia sites as well driving development for failure analysis capabilities for AMD products. He holds a Masters of Science (Microelectrics) from National University of Singapore. He has authored or co-authored more than 20 papers and holds 3 patents. He was the General Chairman of IPFA 2012 in Singapore and the co-General Chairman of IPFA 2011 conference held in Incheon, South Korea in 2011. Papers that he has authored or co-authored has won Best Paper at ISTFA (2000) and IPFA (2009) as well as Best in Session at ISTFA (2001). He has participated in IRPS and ISTFA as authors and IPFA conferences as author, committee member, session chair, Technical Chair. He is current a member of the EDFAS Magazine Editorial Committee.

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Committee Member

Pey Kin Leong; SUTD

Dr. Pey Kin Leong is currently the Associate Provost (Education) of the Singapore University of Singapore. He received his Bachelor of Engineering (1989) and Ph.D (1994) in Electrical Engineering from the National University of Singapore. He has held various research positions in the Institute of Microelectronics, Chartered Semiconductor Manufacturing, Agilent Technologies and National University of Singapore. He was previously Head of the Microelectronics Division, Program Director of the Si Technology Research group, Laboratory Supervisor of the Micro Fabrication Facility, and the Director of the Microelectronic Center in the School of Electrical & Electronics Engineering, Nanyang Technological University, Singapore.

Dr. Pey is a senior member of IEEE and an IEEE EDS Distinguished Lecturer, and has been the organizing committee member of IPFA since 1995. He was the General Chair of IPFA2001, Singapore and the co-General Chair of IPFA2004, Hsinchu, Taiwan. KL Pey was the Guest Editor of IEEE Transactions on Devices in and Materials Reliability in 2003-05 and 2007, and the Chair of the Singapore IEEE REL/CPMT/ED Chapter in 2004/05, and served on the 2006/07/08 IRPS technical subcommittee, and the IPFA’02 to IPFA’06 and IPFA’08 technical committee, and the 2007 IEDM CMOS & Interconnect Reliability and 2008 IEDM Characterization, Reliability and Yield sub-committee.

Dr. Pey has published more than 185 international refereed publications (including 7 invited papers and one review article) and 170 technical papers at international meetings/conferences (including 24 invited talk), and holds 38 US patents. Dr. Pey has contributed significantly to the CMOS gate dielectric reliability, especially in the areas of physical analysis of ultra-thin dielectric breakdown mechanism.

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Committee Member

Vinod Narang; AMD

Mr Vinod has been working with Device Analysis lab AMD, Singapore since 2005. He is team leader of Silicon level failure analysis group and working on New Product Bring-up, Reliability Qualification and Yield Improvement of advanced Microprocessor products based on 28nm and advanced FINFET technology nodes.

Prior to joining AMD, he has worked with TECH Semiconductor, a Micron Technology JV DRAM wafer fab on product yield failure analysis for various process technologies from 180nm to 110nm. His areas of interest include advanced failure analysis tools and techniques development, plasma and wet etch based recipe development and physical fault isolation techniques.

Mr Vinod obtained Master’s Degree in Advanced Materials with focus on Microelectronics from NUS-MIT Alliance program in 2000, and graduated from Flex Time MBA program with Dean’s list from SMU in 2011. He has published / presented more than 30 technical papers. He has given invited talks at Zeiss Workshop; NMC, Singapore and Microelectronics Tech Asia. He has also given a webinar organized by Multiprobe, US. Vinod is actively involved with IEEE International Symposium on The Physical and Failure Analysis of Integrated Circuits (IPFA) Conference and has served in organizing committee in various roles since 2012. He served as Conference Chair for IPFA 2016 held at MBS, Singapore. He is International Chair for ASM ISTFA Conference for 2017. He is father of 2 young and energetic kids and lives in eastern part of Singapore.

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Committee Member

Ranjan Rajoo; GLOBAL FOUNDRIES

Ranjan is currently a Member of Technical staff , OSAT supply chain management / turnkey engineering with Globalfoundries. Prior to joining he was researcher with A-star Institute of Microelectronics (IME) for 15 years in Microsystem, Design & Simulation task. His area of research was 2.5D, 3DIC using TSVs, ultra thin chip embedding and wafer level packaging. His expertise are characterisation of mechanical & moisture properties of electronics packaging materials. He has set up new & novel experimental techniques to characterise electronics packaging materials, assembly process interaction & accelerated reliability, drop, impact and vibration testing.
He has authored and co-authored more than 60 papers in journal and international conferences. He received 2 outstanding papers in prestigious conferences. He has given invited talks in the area of lead free solder/ Halogen Free printed circuits boards. Currently, he holds 6 U.S patents and 2 patents have been commercialised. He is also a member of IEEE, CPMT and IMAPS societies. He was a General chair for IEEE EPTC 2016.

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Committee Member

Nagarajan Raghavan; Singapore University of Technology and Design

Nagarajan Raghavan is an Assistant Professor at the Singapore University of Technology and Design (SUTD) in the Engineering Product Development pillar. Prior to this, he was a postdoctoral fellow at the Massachusetts Institute of Technology (MIT) in Boston and at IMEC in Belgium. He obtained his Ph.D. (Microelectronics, 2012) at the Division of Microelectronics, Nanyang Technological University (NTU), Singapore. His work focuses on statistical characterization and reliability modeling of dielectric breakdown and resistance switching in novel high-κ dielectric material based logic and memory device stacks. He is the recipient of the IEEE EDS Early Career Award for 2016, Asia-Pacific recipient for the IEEE EDS PhD Student Fellowship in 2011 and the IEEE Reliability Society Graduate Scholarship Award in 2008. To date, he has authored / co-authored more than 150 international peer-reviewed publications and five invited book chapters as well. He is currently a Member of IEEE (2005-present) and was an invited member of the IEEE GOLD committee (2012-2014).

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Committee Member

Wong Wui Weng; Advanced Micro Devices

Mr. Wong, Wui Weng is currently a Senior Member of Technical Staff in AMD, Singapore. Graduated from Arizona State of University with Master of Science in Electrical Engineering, he joined Compaq Computer as a Hardware Engineer in Singapore Design Centre. From year 2000, he started his engineering career in Singapore AMD focusing in electrical characterization and analysis for packaging technologies. His main interests are signal integrity measurements and simulations from interconnects component to platform channels. He has been actively involved in technical paper publications and conference organization in Asia. Serving as a chair in technical committee of EPTC for years and he became General Chair of EPTC 2019.

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