SF Bay Area Nanotechnology Council

IEEE

Sept 15th, 2020: The Era of Hyperscaling in Electronics

The Era of Hyperscaling in Electronics

Prof.  Suman Datta, Stinson Chair Professor of Nanotechnology, University of Notre Dame

Tues Sept 15, 11:30 AM – 1:30 PM : Online Check-in 11:30 AM – 12 Noon; Seminar 12 Noon – 1:30 PM

Online (Zoom) FREE Event! Register HERE

Abstract: 

Heterogeneous Integration Fabric

In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach sub-10 nanometer, it is apparent that room for further scaling in the horizontal plane is running out. Further, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. In this talk, I will discuss how electronics is poised to enter a new, third, era of scaling – hyperscaling – in which resources are added in a flexible way when needed to meet the demands of data abundant workloads. This era will be driven by advances in embedded non-volatile memories, hybrid devices with merged logic and memory functionalities, monolithic three-dimensional integration, and heterogeneous integration techniques.

Biography:

Suman Datta is the Stinson Chair Professor of Nanotechnology in Department of Electrical Engineering at the University of Notre Dame. Prior to that, he was a Professor of Electrical Engineering at The Pennsylvania State University, University Park, from 2007 to 2011. From 1999 till 2007, he was in the Advanced Transistor Group at Intel Corporation, Hillsboro, where he developed several generations of high-performance logic transistor technologies including high-k/metal gate, Tri-gate and non-silicon channel CMOS transistors. His research group focuses on emerging devices that enable new computing models. He is a recipient of the Intel Achievement Award (2003), the Intel Logic Technology Quality Award (2002), the Penn State Engineering Alumni Association (PSEAS) Outstanding Research Award (2012), the SEMI Award for North America (2012), IEEE Device Research Conference Best Paper Award (2010, 2011) and the PSEAS Premier Research Award (2015).  He is a Fellow of IEEE and the National Academy of Inventors (NAI). He has published over 350 journal and refereed conference papers and holds 185 patents related to semiconductors. He is the Director of a multi-university advanced microelectronics research center, called the ASCENT, funded by the Semiconductor Research Corporation (SRC) and the Defense Advanced Research Projects Agency (DARPA). He will serve as the General Chair of the 2020 IEEE International Electron Device Meeting (IEDM).

One Response to “Sept 15th, 2020: The Era of Hyperscaling in Electronics”

  1. ctran says:

    We have allowed posting slides from this talk! They are now uploaded onto the “Events Archive” webpage.