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Physics of Failure vs Standards Based Qualification

August 13, 2020 @ 12:00 pm - 1:00 pm

Dr. Preeti Chauhan (IEEE distinguished lecturer)

 

Abstract

Electronics industry is going through an extensive roadmap change with increased complexity, evolving use conditions, and accelerated time to market. Moreover, these characteristics are very different for Electronic devices intended for the mobile segment, client segment and server computing segment. In fact, distinct use conditions and requirements exist within individual segments. Case in point are the server and cloud computing microprocessors that cater to multiple markets such as Scalable Performance, High Performance Computing, Customized Multi-chip Packages, and Advanced Driver Assistance Systems (ADAS). Hence, the qualification for these different market segments cannot be a one-size fits all approach, aka Standards Based Qualification (SBQ).

SBQ proposes a set of reliability requirements based on the historical database of use conditions and reliability data. While SBQ simplifies and standardizes the product qualification, it often grossly over or under estimates the end of life requirements of products. The delta is widening increasingly due to the addition of new and more complex architectures, use conditions, and the need for faster time to market.

Physics of Failure (PoF) or Knowledge Based Qualification (KBQ) approach offers a more practical and focused solution to aforementioned challenges. KBQ utilizes the key technology attributes of the semiconductor packages and employs the fail mode specific reliability models to provide a qualification approach that can be tailored to the specific use condition. KBQ is a paradigm shift from “standard” to “customized” qualification methodology, wherein it ropes in the considerations of cost, product volumes, architectural complexity, use conditions, and time to market, in the qualification methodology. At the same time, the development of prognostics have enriched the KBQ methodology with new Prognostics and Health Management (PHM) techniques to enable better and faster qualification of products. KBQ not only provides use condition specific end of life requirements in reliability testing, but also enables the feedback loop for specific design, process and material attribute changes to enable faster selection and development of robust technologies.

 

Bio

Dr. Preeti S. Chauhan is Technical Program Manager (TPM) in Data Center Quality at Google where she manages the quality and reliability of storage and main memory devices in the data center fleet. Before joining Google, she was a TPM for quality and reliability in the Assembly Test and Technology Development division at Intel Corporation and managed the certification of Intel’s server processors and SOCs.

Preeti received Ph.D in Mechanical Engineering from University of Maryland, College Park in Dec 2012. Her research focused on the reliability of lead-free solder interconnects, copper wire bonding and prognostics and health management of electronics. She authored a book on the challenges and technology enablers for Copper Wire Bonding in 2013, as well as several book chapters in the area of reliability of electronic packages, and PHM. DR. Chauhan has published more than twenty refereed articles in high impact journals and conferences and has also been involved in peer review of journal articles for Microelectronics Reliability and Transactions on Material Device Reliability.

Preeti received the Early Career Award from James Clark School of Engineering at University of Maryland, College Park in recognition of her professional achievements at an early stage of career. She is also the recipient of Intel Achievement Award – Intel’s highest honor for contribution to development of industry first 3-D packaging technology for microprocessors.

Preeti is a member of IEEE and currently serving as the vice president of the technical activities committee in the IEEE Reliability Society. She is also an editorial board member of the Computer Society co-managing the data column.

Dr. Preeti S. Chauhan is Technical Program Manager (TPM) in Data Center Quality at Google where she manages the quality and reliability of storage and main memory devices in the data center fleet. Before joining Google, she was a TPM for quality and reliability in the Assembly Test and Technology Development division at Intel Corporation and managed the certification of Intel’s server processors and SOCs.

Preeti received Ph.D in Mechanical Engineering from University of Maryland, College Park in Dec 2012. Her research focused on the reliability of lead-free solder interconnects, copper wire bonding and prognostics and health management of electronics. She authored a book on the challenges and technology enablers for Copper Wire Bonding in 2013, as well as several book chapters in the area of reliability of electronic packages, and PHM. DR. Chauhan has published more than twenty refereed articles in high impact journals and conferences and has also been involved in peer review of journal articles for Microelectronics Reliability and Transactions on Material Device Reliability.

Preeti received the Early Career Award from James Clark School of Engineering at University of Maryland, College Park in recognition of her professional achievements at an early stage of career. She is also the recipient of Intel Achievement Award – Intel’s highest honor for contribution to development of industry first 3-D packaging technology for microprocessors.

Preeti is a member of IEEE and currently serving as the vice president of the technical activities committee in the IEEE Reliability Society. She is also an editorial board member of the Computer Society co-managing the data column.

Details

Date:
August 13, 2020
Time:
12:00 pm - 1:00 pm