IEEE Tutorial on LDPC Decoding, Aug 2013

IEEE Tutorial on LDPC Decoding, VLSI Architectures and Implementations

Speakers: Dr. Ned Varnica, Marvell Semiconductor and Dr. Kiran Gunnam, NVIDIA

Time: 7:00 pm -9:30 pm Wednesday, August 14 2013


Flash Memory Summit Conference, Santa Clara Convention Center, Santa Clara

Register at Eventbrite

Register for exhibits at


Ned and Kiran’s tutorial presentations on the Flash Memory Summit conference :





LDPC codes are now being used in Hard disk drive read channels, Wireless (IEEE 802.11n/ IEEE 802.11ac, IEEE 802.16e WiMax), 10-GB, DVB-S2, and more recently in Flash SSD. Tutorial’s target audience is system engineers and design engineers. Tutorial has two parts, first module is focused on LDPC Decoding and second module is focused on VLSI Architectures and Implementations.


Tutorial overview

Module 1 LDPC Decoding

1.1) LDPC codes

1.2) Hard decision decoding,

1.3) LLR basics and LLR generation for soft decoding for Flash memory channel

1.4) Soft decoding and Min-Sum Algorithm

1.5) LDPC decoder performance characteristics, trapping sets and error floor

1.6) Basics of Code Structures for Efficient hardware.



Module 2 VLSI Architectures and Implementations

2.1) Check Node Unit Design and Value-reuse property

2.2)   Non-layered decoder architecture

a)   Block serial processing

b)  Translating throughput requirement to H matrix parameters and edge parallelization

2.3)  Layered decoder architecture

a) Block serial processing

b) Block serial processing for irregular H matrices, scheduling of decoder processing

c) Block parallel processing

d) Translating throughput requirement to H matrix parameters and edge parallelization

e) Case study of decoders for 802.11n and Flash channel

2.4) Error floor mitigation schemes



Module 1:

Ned Varnica, Marvell Semiconductor


Ned Varnica received the B.S. degree in Electrical Engineering in 2000 from School of Electrical Engineering, University of Belgrade, Serbia, the M.S. degree in 2001 and Ph.D. in 2005 both from Harvard  University, Cambridge, Massachusetts.

Since 2005 he has been with Marvell Semiconductor Inc, Santa Clara, California. He held short-term research positions at Maxtor Corporation, Shrewsbury, Massachusetts in 2002 and Lucent Bell Labs, Murray Hill, New Jersey in 2004. He spent the summer of 2003 as a visiting researcher at University of Hawaii at Manoa, Honolulu. His research interests are in the areas of communication theory, information theory, channel and source coding and their applications to digital data storage and wireless communications.

Dr. Varnica received the Best Student of the Class Award from the Department of Communications at the School of Electrical Engineering, University of Belgrade in 2000.  He is a co-recipient, with A. Kavcic

and X. Ma, of the 2005 IEEE Best Paper Award in Signal Processing and Coding for Data Storage.


Module 2:

Kiran Gunnam, NVIDIA


Kiran Gunnam received the MSEE and PhD in Computer Engineering from Texas A&M University, College Station, TX. He is a lead micro-architect and ASIC designer. He currently works in the Tegra group at NVIDIA. He previously held research and development positions at Certicom, LSI, Marvell Semiconductor, Starvision Technologies, Schlumberger, Intel and Texas Engineering Experiment Station.

Dr. Gunnam has extensive research and development work experience in complex data path and control path systems. His PhD research contributed several key innovations in advanced error correction systems based on low-density parity check codes (LDPC) and led to several industry designs. He has done extensive work on algorithm development for LDPC based error correction systems and their ASIC hardware architecture, micro-architecture and implementation along with the FPGA prototyping for different systems ( IEEE  802.11n Wi-Fi, IEEE 802.16e WiMax, IEEE 802.3 10-GB, Holographic read channel, HDD read channel and Flash read channel).

Dr. Gunnam has around 25 issued patents, 25 pending patents and 27 more invention disclosures. He was elected as IEEE Senior Member in April 2007 for significant contributions in integrated circuit design for signal processing and communication systems. He is also an IEEE Solid State Circuits Society Distinguished Lecturer for 2013 and 2014.


Event Co-sponsors:

Flash Memory Summit

IEEE Professional Activities Committee for Engineers, Santa Clara Valley Section (IEEE SCV PACE)


IMG_0784 IMG_0786IMG_0176 IMG_0168







  • September 2020
    M T W T F S S