Speaker: Prof. David Declercq (ENSEA in Cergy-Pontoise)
Please note special starting time for this event:
Event Time: June 28th(Thursday) 5PM-9PM
Networking and snacks : 5:00 PM: 5:15 PM;
Lecture Time, Session 1 : 5.15 PM- 7.00 PM;
Break : 7.00PM- 7.15PM ;
Lecture Time, Session 2 : 7.15 PM -8.30 PM
Overflow questions : 8:30 PM -8.50 PM ;
Event conclusion : 8.50PM -9 PM
Texas Instruments Silicon Valley Auditorium
(formerly National Semiconductor Auditorium E)
General information on Tutorial:
A low-density parity-check (LDPC) code is a linear error correcting code, a method of transmitting a message over a noisy transmission channel. LDPC codes are finding increasing use in applications requiring reliable and highly efficient information transfer over bandwidth or return channel–constrained links in the presence of data-corrupting noise. LDPC is now being used in Hard disk drive read channels, Wireless (IEEE 802.11n/ IEEE 802.11ac, IEEE 802.16e WiMax), 10-GB, DVB-S2, and more recently in non-volatile memory(such as Flash SSD, MRAM, RRAM). Tutorial’s target audience is system engineers and design engineers.
“In this tutorial, the iterative decoding techniques for non-binary LDPC codes will be presented, both from the theoretical aspects of Belief Propagation and its analysis, and from more practical aspects of efficient implementation. In a first part, introduction on error correction coding with LDPC will be presented, and the main differences between iterative BP decoding of binary and non-binary LDPC codes will be highlighted. Then, in a second part, the recent solutions proposed in the literature to reduce the complexity of non-binary decoders, both for memory storage and computational burden reduction, will be presented. Finally, in a third part, some applications where non-binary LDPC codes show their best potential will be discussed.”
David Declercq was born in June 1971. He graduated his PhD in Statistical Signal Processing 1998, from the University of Cergy-Pontoise, France. He is currently full professor at the ENSEA in Cergy-Pontoise, and CTO of Codelucida©, LLC. He is the general secretary of the National GRETSI association, and Senior member of the IEEE. He is currently the recipient of junior position at the “Institut Universitaire de France”.
His research topics lie in digital communications and error-correction coding theory. He worked several years on the particular family of LDPC codes, both from the code and decoder design aspects.
Since 2003, he developed a strong expertise on non-binary LDPC codes and decoders in high order Galois fields GF(q), with q>>2. A large part of his research projects are related to non binary LDPC codes. He mainly investigated two directions: (i) the design of GF(q) LDPC codes for short
and moderate lengths, and (ii) the simplification of the iterative decoders for GF(q) LDPC codes with complexity/performance tradeoff constraints.
This tutorial is part of Training Program Series on Emerging Technologies, organized by PACE with the support of technical society chapters. This program’s objective is to educate IEEE members in the Silicon Valley on emerging technologies.
IEEE Santa Clara Valley(SCV) Section’s Professional Activities Committee for Engineers (PACE), promotes the professional interests of IEEE’s U.S. members and provides a mechanism for communication of members’ views on their professional needs. Activities include Technical Training courses, Workshops on career issues (networking, career planning, career transitions, personal financial planning); skill training workshops (entrepreneurship, effective speaking, technical writing), and Government Policy as it affects Engineering and Technology.
The SCV, more popularly known as Silicon Valley, is the largest IEEE Section in the world in terms of membership (around 12,000 members in Santa Clara Valley Section)as well as active chapters.
The SCV SSCS Chapter has the largest membership of any SSCS Chapter in the world with over 2000 members. 35 members are IEEE Fellows (11 are Life Fellows), 57 are IEEE Life members (8 are Senior Life members) and 132 are IEEE Senior Members. We hold 8-11 technical meetings every year. Our speakers are experts from industry, Professors or Ph.D. candidates from renowned educational institutions or IEEE Distinguished Lecturers. The emphasis in our presentations is on practical IC design, device modeling and CAE tools.
The Santa Clara Valley Chapter of the IEEE Circuits and Systems Society focuses on the theory, analysis, design, practical implementation of circuits, and the application of circuit theory to systems and signal processing in industry and academia. The Chapter provides a forum where participants can network, learn and exhange ideas in a welcoming professional environment.