Accelerating Analog Design


Speaker:  S. S. MohanSynopsys

In association with:

IEEE SCV Solid State Circuits Society (SSCS)


Texas Instruments Building E Auditorium
2900 Semiconductor Dr., Santa Clara, CA 95051.    Directions and Map.

Event Time: October 18th (Thursday), 6 PM – 9 PM




We investigate state-of-the art technology that accelerates analog design by automatically custom sizing an architecture to satisfy specifications for a chosen process over process, voltage and temperature (PVT) variations.  The talk begins with an overview of manual and automated circuit design methods and identifies the iterative and time-intensive steps that result in the analog bottleneck.  We then describe how an equation-based optimizer and optimization friendly process-models are combined with a unified system and circuit formulation that is independent of specification and process to enable analog/RF circuits to be designed and ported efficiently while also documenting the operation of the circuit.  Then, innovations and ease-of-use features that address difficulties associated with traditional equation based optimization methods are presented.  The talk concludes with illustrative applications of commercial equation-based optimization tools in ADC, PLL, RF LCO, opamp, regulator and Serdes designs to highlight how this compelling methodology is leveraged for  process and corner aware, simultaneous optimization of system and circuit across different levels of hierarchy and abstraction.



Speaker’s  Bio:

S. S. Mohan received the B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University, where he focused on the design and optimization of CMOS analog and RF circuits.  He has twenty years experience in circuit design and automation and has designed GPS chips, medical electronics, Serdes RF LCOs and multi-phase VCOs, gigabit-ethernet front-ends and shunt-peaked amplifiers.  He served as Chief Scientist at Sabio Labs prior to its acquisition by Magma Design Automation where he became Senior Director in charge of the analog and mixed-signal circuit design group.  He has taught analog design classes at Stanford as a teaching assistant and visiting faculty and received the Centennial Award for Teaching.  Mohan currently leads the circuit team at Synopsys that creates reusable PLL, ADC, Serdes, RF LCO, Bandgap, Opamp and regulator FlexCells leveraging its proprietary optimizer (ADX).



Event Organizers:

This tutorial is part of Training Program Series on Emerging Technologies, organized by PACE with the support of technical society chapters. This program’s objective is to educate IEEE members in the Silicon Valley on emerging technologies.

IEEE Professional Activities Committee for Engineers,Santa Clara Valley Section (IEEE SCV PACE)

IEEE Santa Clara Valley(SCV) Section’s  Professional Activities Committee for Engineers (PACE), promotes the professional interests of IEEE’s U.S. members and provides a mechanism for communication of members’ views on their professional needs. Activities include Technical Training courses, Workshops on career issues (networking, career planning, career transitions, personal financial planning); skill training workshops (entrepreneurship, effective speaking, technical writing), and Government Policy as it affects Engineering and Technology.

The SCV, more popularly known as Silicon Valley, is the largest IEEE Section in the world in terms of membership (around 12,000 members in Santa Clara Valley Section)as well as active chapters.



Organized by: IEEE SCV PACE


Kiran Gunnam


Career and  Networking Chair, Treasurer: Neeta S Srivastav

Publicity Chair: Manuel Ilagan                                                 

Social Networking Chair and Webmaster: Sanjeev Murthy

Technical Program Chair: Jean-François Merckling

  • August 2020
    M T W T F S S