Title : Generative surrogate models with machine learning methods for real-time digital twins simulation of high-speed channels
Abstract :
This talk will be focusing on using generative models to accelerate high speed channel analysis and optimization. We will start with a brief introduction of Bayesian surrogate models and how to solve the problem of curse of dimensionality that limits the performance of them.
We will show how this machine learning surrogate models can outperform conventional channel optimization techniques and allow real time detection of channel conditions and optimization.
The current state of the art generative models are generative adversarial networks. It consists of a generator which will output analysis result without knowing the underlying details of the modelling circuits.
Instead, it utilizes reinforce learning with a competing discriminator that plays a game of one better than the other with the generator. We will show how these deep learning models can generate eye diagrams that are indistinguishable from real measurements.
Bio
Chris Cheng is a Distinguished Technologist at the Storage Division of Hewlett-Packard Enterprise. He is responsible for managing all high speed, analog/mixed signal designs and hardware machine learning development within the Storage Division. He also held senior engineering positions in SUN Microsystems where he developed the original GTL system bus with Bill Gunning. He was a Principal Engineer in Intel where he led high speed processor bus design team. He was the first hardware engineer in 3PAR and guided their high-speed design effort until it was acquired by Hewlett Packard.
Admission Fee:
All admissions free. Suggested donations:
Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3
Date and time
Thursday, August 25th, 2022, 6:00 PM – 7:00 PM PDT
Location
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Meeting ID: 830 1318 9919
Passcode: 282838
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