Abstract:

A key component of RF systems is on-chip inductors which occupy a significant portion of RF integrated circuits. As CMOS technology is scaled down, the percent area occupied by on-chip inductors has been increasing. On-chip inductors in typical foundry processes have low quality factor and usually are designed without space constraints to maximize quality factor because the inductor area scales with operating frequency not with the minimum feature size of technology. For instance, it has been suggested in 45-nm CMOS, an inductor for a 900-MHz voltage-controlled oscillator occupies an area of a microcontroller core. In this seminar, we will look at approaches to reduce area of high-performance VCOs. The approaches will be verified by design of two VCOs operating at 4.3-5.6 GHz and 16-19GHz with divide-by-4 frequency divider in 65nm digital process.

Speaker’s Bio:

Amit Jha is a senior RF/Wireless engineer at Renesas Electronics where he is developing mm-wave/high speed circuits for 5G and datacom/telecom applications. He received the B.S (’04), MS (’07) and PhD (’16) from the Indian Institute of Technology, Madras, Pennsylvania State University, University Park and University of Texas, Dallas, respectively. From 2016-17, he was with Jazz Semiconductor developing IPs for frontend circuits for 5G applications and from 2007-2010, he was Member of Technical Staff in Maxim Integrated Products, San Jose where he developed compact models for nanoscale CMOS and LDMOS devices. He is a recipient of the best poster award for “VCO Area Reduction in Nano-Scale CMOS Processes” at SRC-TxACE ICSS circuits review, 2014. His research interests include mm-wave circuit design, frequency synthesis and compact modeling of transistors. He is currently the chair of the IEEE Santa Clara Valley Circuits and Systems society and is a Senior Member of IEEE.