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“Scalable Deep Neural Network Accelerator Design and Methodology” by Dr. Prof. Y. Sophia Shao

Date: January 16th, 2020


Sponsored by:

IEEE Silicon Valley Solid-State Circuits Society (SSCS)

IEEE Silicon Valley Circuits and Systems Society (CASS)

“Scalable Deep Neural Network Accelerator Design and Methodology”

Prof. Y. Sophia Shao

University of California, Berkeley

Registration Link: Here.


Machine learning systems are being widely deployed across billions of edge devices and datacenter across the world. At the same time, in the absence of Moore’s Law and Dennard scaling, we rely on building vertically integrated systems with domain-specific accelerators to improve the system performance and efficiency. In this talk, I will describe our recent work on building scalable and efficient hardware that delivers real-time and robust performance across diverse deployment scenarios through joint hardware-software optimizations. I will conclude my talk by describing ongoing efforts toward building next-generation computing platforms for real-time machine learning.


Prof. Y. Sophia Shao is an Assistant Professor of Electrical Engineering and Computer Sciences at the University of California, Berkeley. Previously, she was a Senior Research Scientist at NVIDIA. She received her Ph.D. degree in 2016 and S.M. degree in 2014 from Harvard University and a B.S. degree in Electrical Engineering from Zhejiang University, China. Her research interests are in the area of computer architecture, with a special focus on domain-specific architecture, deep-learning accelerators, and high-productivity hardware design methodology. Her work has been selected as one of the TopPicks in Computer Architecture, a MICRO Best Paper award, and her Ph.D. dissertation was nominated by Harvard for ACM Doctoral Dissertation Award. She is a Siebel Scholar, an invited participant at the Rising Stars in EECS Workshop, and a recipient of the IBM Ph.D. Fellowship.

The seminar is FREE and donation is accepted for refreshments (FREE SSCS/CAS members/$2 IEEE members/$5 non-members)
Eventbrite registration is required for everyone to attend the talk.


Texas Instruments Silicon Valley Auditorium 2900 Semiconductor Dr., Building E, Santa Clara, CA 95051 Directions and Map (to locate Building E).

Time: January 16 (Thursday) evening 6:00PM-8:00PM
Networking and Refreshments: 6:00 PM – 6:30 PM
Technical Talk: 6:30 PM – 8:00 PM

  • January 2020
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