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“VCO Design Challenges And Solutions For Mm-Wave Applications” by Dr. Waleed Khalil

Date: November 1st, 2019

“VCO Design Challenges And Solutions For Mm-Wave Applications”

Dr. Waleed Khalil, ElectroScience Lab, Ohio State University

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section

Co-sponsors:

PROGRAM:

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

No broadcast and no Zoom recording.

REGISTRATION Link:

Here.

Abstract:

Over the past few decades, there has been a plethora of research on VCO architecture and circuit techniques that led to significant improvements across all performance measures. However, with much of the work being directed towards the sub 10 GHz frequency range, there is a need to clearly describe the set of challenges and offer a range of solutions that address the growing interest in mm-Wave systems.

This seminar will present first, at the fundamental level, key challenges that the designer faces when attempting to design and optimize the performance of mm-wave VCOs on silicon technologies.

In the second part, we will describe some of the techniques, that are validated on silicon at circuit architecture and layout levels, that can be utilized to significantly improve the tuning range, phase noise and power efficiency of mm-Wave VCOs, while still meeting the required robustness level. The talk is designed to spur analytical thinking on a variety of mm-Wave VCO design challenges, while also offering a new perspective in addressing these challenges.

Bio:

Waleed Khalil received his B.S. and M.S. degrees from the University of Minnesota and his PhD degree from Arizona State University, all in Electrical Engineering. He is currently serving as an Associate Professor at the ECE department and the ElectroScience Lab, The Ohio State University. Prior to joining OSU in 2009, he spent 16 years at Intel Corporation where he held various technical and leadership positions in wireless and wireline communication groups. At OSU, he leads a multidisciplinary research team in high performance clocking circuits, GHz data converters, digital intensive RF and mm-wave circuits and system as well as heterogeneous integration and hardware trust and assurance. His research group has been recognized with several awards, among them TSMC’s outstanding research award and best paper awards in several conferences. He authored over 100 journal and conference papers, 13 issued and several other pending patents, and three books/book chapters. He is a senior member of IEEE and serves as the general chair for the 2020 RFIC Symposium and as an Associate Editor for the Journal of Solid State Circuits.

Venue:

QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara, CA 95051

 

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.


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