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“Reflections On High-Performance Fractional-N Frequency Synthesis”, by Prof. Peter Kennedy FIEEE & “Sub-Sampling Techniques for mm-Wave and Digital Phase-Locked Loops”, by Prof. Teerachot Siriburanon, University College Dublin, Ireland

Date: February 22nd, 2019

Two Lectures On PLLs:

“Sub-Sampling Techniques For Mm-Wave And Digital Phase-Locked Loops”

Prof. Teerachot Siriburanon, University College Dublin, Dublin, Ireland

“Reflections On High-Performance Fractional-N Frequency Synthesis”

Prof. Peter Kennedy FIEEE, University College Dublin, Ireland

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section



4:30 – 5:00 PM Networking & Refreshments
5:00 – 6:00 PM Lecture 1: “Sub-Sampling Techniques for mm-Wave and Digital Phase-Locked Loops” by Prof. Siriburanon

6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Lecture 2: “Reflections on High-Performance Fractional-N Frequency Synthesis” by Prof. Kennedy
7:45 – 8:00 PM Q&A/Adjourn

Zoom broadcast may not be possible. In person attendance requested.


Lecture 1:


This talks presents the development of low-power and low-phase-noise phase-locked loops (PLLs) using sub-sampling techniques. The method in which gains significant interests in the past decade to apply in low-jitter PLLs. In the first part of the talk, the consideration of architectures for mm-wave frequency generation will be reviewed and the method using sub-sampling phase detection in sub-harmonic injection locked architecture for 60GHz frequency synthesis will be discussed. The design of key building blocks will be presented in order to achieve low power consumption with good performance, e.g. injection-locked frequency divider and mm-wave oscillators. In the second part of the talk, sub-sampling technique is extended for the use in all-digital phase-locked loop in digital sub-sampling architecture. Finally, the methods to extend sub-sampling techniques in fractional-N operation and recent developments in the field will be discussed.


Teerachot Siriburanon received the B.E. degree in Telecommunications Engineering from Sirindhorn International Institute of Technology (SIIT), Thammasat University, Pathumthani, Thailand, in 2010, the M.E. degree and Ph.D. degree in Physical Electronics from Tokyo Institute of Technology, Tokyo, Japan, in 2012 and 2016, respectively. In 2016, he joined University College Dublin (UCD), Dublin, Ireland, as a postdoctoral researcher and later received Marie Skłodowska-Curie Individual Fellowship in 2017. Since 2019, he has been an Assistant Professor with University College Dublin (UCD), Dublin, Ireland.

Dr. Siriburanon was the recipient of the Japanese Government (MEXT) Scholarship, the Young Researcher Best Presentation Award at Thailand-Japan Microwave in 2013, the ASP-DAC Best Design Award in 2014 and 2015, the IEEE SSCS Student Travel Grant Award in 2014, the IEEE SSCS Predoctoral Achievement Award in 2016, and the Tejima Research Award in 2016.

Lecture 2:


Fractional-N frequency synthesizers are widely used in electronic systems to generate carrier or clock frequencies that are not simple integer multiples of a reference frequency. As synthesizer architectures are pushed to the limits of their performance, new insights have been gained into underlying mechanisms for excess noise and spur generation. With these insights come strategies for addressing underlying causes. This lecture presents an overview of fractional-N frequency synthesis, highlighting fundamental architecture-related issues which can degrade performance, insights into the root causes of the problems, and some ideas which help to ameliorate the situation.


Michael Peter Kennedy is Professor of Microelectronic Engineering at University College Dublin and President of the Royal Irish Academy (RIA). He received his PhD from the University of California at Berkeley in 1991 and the DEng from the National University of Ireland in 2010. He has published over 390 technical articles, including monographs and patents, covering “blues skies” to applied research, from chaos theory to circuit design. He received the IEEE Millenium and Golden Jubilee Medals, and the inaugural RIA Parsons Award in Engineering Sciences. He was made a Fellow of the IEEE in 1998 for contributions to the theory of neural networks and nonlinear dynamics and for leadership in nonlinear circuits research and education. From 2005 to 2007, he was President of the European Circuits Society and Vice-President of the IEEE Circuits and Systems (CAS) Society. He was a Distinguished Lecturer of the IEEE during 2012‒13. He is founding Director of the Microelectronics Industry Design Association and Microelectronic Circuits Centre Ireland. He has commercialized efficient test algorithms for data converters, behavioral simulation strategies for PLLs, and architectures for high-performance frequency synthesizers.


Texas Instruments, Building E Conference Center, 2900 Semiconductor Blvd., Santa Clara, CA 95051

Live Broadcast:

Live broadcast may not be available. In person attendance requested.

Admission Fee:

All admissions free. Suggested donations to cover food and water:

Non-IEEE: $5, Students (non-IEEE): $3, IEEE Members (not members of CASS or SSCS): $3

Online registration is recommended to guarantee seating.

  • February 2019
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