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“Holistic Design in Optical Interconnects” Prof. Azita Emami, California Institute of Technology IEEE SSCS Distinguished Lecturer

Date: December 6th, 2018


Sponsored by:

IEEE Silicon Valley Solid-State Circuits Society (SSCS)

IEEE Silicon Valley Circuits and Systems Society (CASS)

IEEE Silicon Valley Electronics Packaging Society (EPS)

“Holistic Design in Optical Interconnects”
Prof. Azita Emami, California Institute of Technology
IEEE SSCS Distinguished Lecturer

Registration Link:

Click here to register.


Texas Instruments Silicon Valley Auditorium 2900 Semiconductor Dr., Building E, Santa Clara, CA 95051 Directions and Map (to locate Building E).

Time: December 6 (Thursday) evening 6:00PM-8:00PM
Networking and Refreshments: 6:00 PM – 6:30 PM
Technical Talk: 6:30 PM – 8:00 PM


The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Today Data Center (DC) and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented.


Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007, she was an Assistant Professor of Electrical Engineering at Columbia University in the city of New York. In 2007, she joined Caltech, where she is now a Professor of Electrical Engineering and Medical Engineering. She is a Heritage Medical Research Institute Investigator, and serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems, high-speed on-chip and chip-to-chip interconnects, system and circuit design solutions for highly-scaled CMOS technologies, wearable and implantable devices for neural recording, stimulation, and efficient drug delivery.

The seminar is FREE and donation is accepted for refreshments (FREE SSCS/CAS members/$2 IEEE members/$5 non-members)
Eventbrite registration is required for everyone to attend the talk.


Lecture by Dr. Hans Klein: “Advanced Capacitive Sensing for Consumer, Industrial, and Automotive Applications”

Date: December 6th, 2018


“Advanced Capacitive Sensing for Consumer, Industrial, and Automotive Applications”

Dr. Hans Klein, Analog CTO, Cypress Semiconductor Corp., San Jose

Event Organized By:

Circuits and Systems Society (CASS) of the IEEE Santa Clara Valley Section



6:00 – 6:30 PM Networking & Refreshments
6:30 – 7:45 PM Talk
7:45 – 8:00 PM Q&A/Adjourn

Watch the lecture live on Zoom from your home and anywhere around the world! Register now and you will be sent details one day before the event.

Registration Link:

Click here to register.


This presentation reviews basic and advanced capacitive sensing for a variety of consumer, industrial, and automotive applications. Examples include “single-pixel” buttons, sliders, touch screens, and “kilo-pixel” fingerprint readers. To enable this, advanced embedded capacitance-sensing technology handles signals from the pF range all the way to fractions of an aF. In this context, challenges and solutions for sensors, architectures, algorithms, and circuit technology are discussed.


Hans received a Ph.D. for his contributions in the Analog Circuit domain from the Technical University of Aachen, Germany, in 1983. In ‘84 he joined the founding-team of the Institute for Microelectronics, Stuttgart, Germany, where he developed a number of mixed-signal ICs for audio, sensing, and control applications.

In ‘88 he joined IMP Inc. in San Jose, CA, where he focused on structured analog Design-Methodology and low-noise mixed-signal CMOS design, including the world’s lowest-noise CMOS Read-Channel IC.

He then served at Lattice Semiconductor as Director of Design, where he developed the “PAC” family of programmable analog products. And in 2004 he joined start-up GTronix as VP-Eng, focusing on microWatt analog signal-processing technology using floating-gate CMOS.

In 2009 Hans joined Cypress Semiconductor as Analog CTO, driving a new generation of embedded programmable analog subsystems and driving research in Cap-Sense, Touchscreen, and Fingerprint-sensing technology. Now a Sr. VP Fellow, he also manages the corporate Innovation Program. Hans has over 50 patents.


Cypress Semiconductor Corporation, Main Auditorium in Building 6, 198 Champion Ct, San Jose, CA 95134

Convenient VTA light rail access from Mountain View and downtown San Jose.

Live Broadcast:

Lecture will be broadcast live on Zoom. Registrants will be sent the conference details one day before the event.

Admission Fee:

Open to all to attend
Online registration is recommended to guarantee seating.

You do not need to be an IEEE member to attend.

  • December 2018
    M T W T F S S