Next Event

No event scheduled. Check back soon!


Want to volunteer?

The IEEE SCV CAS chapter is seeking volunteers to help with the organization of technical meetings. Please contact us.


SCV-CAS Mailing List

To subscribe or unsubcribe, please visit the IEEE SCV-CAS list.

RISC-V Software Ecosystem and Hardware Framework for Faster Silicon Realization

Date: November 14th, 2018


RISC-V is a free and open Instruction Set Architecture enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for future computing design and innovation.

In the true spirit of Chip Chat, which brings hardware, software, system and application designers together, our November event has talk on “Software State of the Union” for RISC-V ecosystem by an excellent speaker Palmer Dabbelt, from SiFive and ” Hardware Frameworks for building custom silicon faster” by Rajesh V, also from SiFive.

Topic : “Software State of the Union” for the RISC-V ecosystem

Speaker : Palmer Dabbelt

Bio : Palmer is currently the RISC-V Software Team Lead at SiFive, where he maintains the RISC-V ports of binutils, GCC, glibc, Linux, and QEMU. Palmer got involved in the RISC-V project when he was a graduate student at UC Berkeley, where he worked on a pair of RISC-V chips and contributed to the RISC-V software ecosystem. He began his career at Tilera, where he spent most of his time working on a port of Sun’s HotSpot Java virtual machine to a pair of Tilera’s ISAs. In addition his MS in Computer Science from UC Berkeley, Palmer holds a BS in Electrical Engineering from the University of Illinois.

Topic : ” Hardware Framework to Enable Faster Idea-to-Silicon Realization”

Speaker : Rajesh V

Bio : Rajesh Varadharajan is currently the Director of Applications engineering at SiFive responsible for configuring and delivering the custom RISCV cores to the customers. Around 14+ years of experience In ASIC and FPGA design, Rajesh started his career in Rambus as ASIC Engineer working on Ethernet, PCIExpress IPs. After a start stint in SanDisk as Application Engineer where he was building INAND validation platforms, he moved back to Rambus Cryptography Division where he was responsible for designing the Consumable crypto firewall chip. Rajesh received his bachelors from University of Madras , India and finished his masters in Vellore Institute of Technology, India

6:30pm – 7:00pm – Registration and Networking
7:00pm – 8:00pm – Tech Talks
8:00pm – 8:30pm – Networking

Registration Link: here

1. Suggested donation is 10/- to cover the expenses.
– Cash
– Venmo to
– Onsite Credit Card payment

2. Confidential Information will not be discussed. Audience is requested
to refrain from asking questions related to confidential information.



– Please register as soon as possible before we run out of space

– Please mark your calendars and do not miss this Chip Chat event


Thanks to Palmer Dabbelt and Rajesh for readily accepting our invitation to give the talk.

Special thanks to IEEE SVC Young Professionals for co-hosting this event.

Chip Chat Committee : Rambabu Pyapali, Hari Sathianathan, Sriram Radhakrishna, Wenbo Yin, Sukriti Kapoor and Nihita Sadhana

  • November 2018
    M T W T F S S