IEEE Circuits and Systems Society-Silicon Valley (CAS-SV) Artificial Intelligent For Industry Forum
Topic:
Algorithm-architecture co-design for energy-efficient deep learning, including algorithm optimization (e.g., novel numerical representation, network pruning/compression) and accelerator architectures (e.g., programmable SoC).
Eventbrite Registration Link:
Location:
Intel Santa Clara SC12 Auditorium
3600 Juliette Ln, Santa Clara, CA 95054
Time: 1:00 PM – 5:00 PM PDT
Schedule:
(1) 1.30-2.15pm Architecture for Machine Learning, Dr. Debbie Marr, Sr. Principal Engineer and Director, Intel Labs, Intel Corporation
(2) 2.15-3.00pm Energy-Efficient Edge Computing for AI-driven Applications, Prof. Vivienne Sze from MIT, Associate Professor of Electrical Engineering and Computer Science, Electrical Engineering and Computer Science, (http://www.rle.mit.edu/people/directory/vivienne-sze/)
(3) 3.20-4.05pm MobileNet: designing efficient architectures for mobile classification, detection and segmentation, Dr. Mark Sandler, Google
(4) 4.05-4.50pm Deep Learning Inference in Facebook Data Centers: Characterization, Performance Optimizations, and Hardware Implications, Dr. Jongsoo Park, Facebook
Abstract:
In this talk we present lessons and insights that led us to design of MobileNet V1 and V2, discuss common optimization techniques, such as quantization, and common pitfalls when designing efficient architectures as well show our insights can guide automated architecture search.
Host:
IEEE Circuits and Systems Society and Intel Corporation
Co-Host: IEEE Circuits and Systems Society Santa Clara Valley Chapter, IEEE Signal Processing Society Santa Clara Valley Chapter, and IEEE Computer Society Technical Committee on Multimedia Computing
Presentation Slides:
Debbie Marr, “Architecture for Machine Learning”
Vivienne Sze, “Energy-Efficient Edge Computing for AI-driven Applications”
Mark Sandler, “Designing Efficient Architectures for Mobile Computer Vision”
Jongsoo Park, “Deep Learning Inference in Facebook Data Centers: Characterization, Performance Optimizations, and Hardware Implications“