Design-for-Reliability and Accelerated Testing of Solder Joint Interconnections in Medical Electronics
Dr. EPHRAIM SUHIR
Bell Laboratories, Physical Sciences and Engineering Research Division, Murray Hill, NJ, USA (ret);
Portland State University, Depts. of Mech. and Mat., and Elect. and Comp. Engineering, Portland, OR, USA;
Technical University, Dept. of Applied Electronic Materials, Inst. of Sensors and Actuators, Vienna, Austria;
James Cook University, Mackay Institute of Research and Innovation, Townsville, Queensland, Australia;
ERS Co., 727 Alvina Ct., Los Altos, CA 94024, USA, www.ERSuhir.com
Date: Wednesday, March 11th, 2020
Time: 4:00 PM – 6:00 PM
Followed by coffee and refreshments in Shannon Room, Engineering IV.
1) Several novel and promising approaches that enable evaluating the expected reduction in the stress level and in the bow (warpage) of the assembly, and to determine, based on the computed data, what could possibly be done to reduce stresses in, and deformations of, the solder joints of both levels of interconnections.
2) The probabilistic DfR (PDfR) concept is suggested and applied with an intent to predict, based on the highly focused and highly cost-effective failure-oriented-accelerated testing (FOAT) conducted for the considered SJI system, weather of flip-chip type or ball-grid-array (BGA) type or column-grid-array (CGA) type.
3) Less costly, less time and labor consuming and, most importantly, more physically meaningful test vehicle other than temperature cycling is introduced. Traditional Temperature cycling is costly, time- and labor consuming, but, most importantly, can result in misleading information, since testing is done, as a rule, in a wide temperature range, much wider than what the material might encounter in actual operation, and, as is known, material’s properties are temperature dependent. Because of that, a clear motivation that would be more physically meaningful. Since the highest stresses occur in SJIs at low temperature conditions and crack propagation is accelerated by random vibrations, especially at low temperature conditions, a low-temperature/random-vibrations bias is suggested as an attractive substitute for temperature cycling accelerated tests, especially for automotive applications, when such a bias reflects the actual loading conditions in the field. This approach has been reduced to practice under a project with NASA JPL.
Ephraim Suhir is Life Fellow of the Institute of Electrical and Electronics Engineers (IEEE), the American Society of Mechanical Engineers (ASME), the Society of Optical Engineers (SPIE), and the International Microelectronics and Packaging Society (IMAPS); Fellow of the American Physical Society (APS), the Institute of Physics (IoP), UK, and the Society of Plastics Engineers (SPE); and Associate Fellow of the American Institute of Aeronautics and Astronautics (AIAA). This year he received the 2019 IEEE Electronic Packaging Society (EPS) Field award for seminal contributions to mechanical reliability engineering and modeling of electronic and photonic packages and systems and Int. Microelectronic Packaging Society’s (IMAPS) Lifetime Achievement award for making exceptional, visible, and sustained impact on the microelectronics packaging industry and technology.
For more information, contact Guangqi Ouyang at email@example.com
Or go to IEEE EPS/EDS Student Chapter at UCLA website: https://site.ieee.org/sb-ucla-eped/