IAS Webinar on FPGA Designing

An online workshop FPGA(Filed Programmable Gate Array)
design using Vivado design suite was conducted by RSET
Industry Applications Society Student Branch Chapter on
Google meet platform. The session was handled by Mr .B
EDMOND BARNABAS ENOCK, Assistant Professor, College of
Engineering Munnar. 37 participants were registered for the
event and we got 23 active participants throughout the
workshop. Vivado design suite software was introduced to
the participants and discussed about various tools in it.
Detailed explanations about programmable gates and FPGA
were given. It was a 1 hour learning session. Students were
able to understand what is FPGA and design them using
Vivado design suite .

Posted in SB Events.

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