31 May 2022 – 5.00 PM
Politecnico di Torino – Maxwell Room
Please, remember that registration is required to attend the event.
The ever-increasing demand for compute power and data processing in accelerators, GPUs, telecommunication networks and mobile devices is requiring wireline and radio frequency transceivers to operate at increasing bandwidths, exacerbating the channel losses. Recent advances in ADCs have enabled the use of DSP techniques to combat sever channel loss and impairments.
In this talk an introduction to DSP-based SerDes will be covered, with a focus on the digital design challenges.
Darjn Esposito is currently a Senior ASIC Digital Design Engineer at Synopsys, where he is working on the design of high-speed SerDes PHYs. Previously he has worked both in academia and in industry, mainly in the areas of DSP and approximate arithmetic circuits.
Matteo Pisati is currently R&D Director at Synopsys, where he is leading the Pavia design center. He has 20+ years’ experience in the SerDes field, starting from the M.S. and Ph.D. degrees at University of Pavia (’01, ‘05), going through his experience in the industry, from STMicroelectronics till to Synopsys.