PitchD 2024 edition: the 1st PitchD [UPDATE: event material available!]

4th March 2024 – 5.00 PM
Politecnico di Torino – Maxwell Room

Here’s the 1st PitchD – the PhD’s pitch. Our PhD IEEE Student Members explain to students, colleagues and professors their research in-presence. Please, remember that registration is required to attend the event.

Estimating the reliability of DNNs in the face of permanent GPU hardware failures

Mr. Juan Balaguera
Dept. of Department of Control and Computer Engineering, Politecnico di Torino

Biography:Juan David Guerrero Balaguera received his bachelor’s and master’s degrees in Electronics Engineering from the Universidad Pedagógica y Tecnológica de Colombia (UPTC), Sogamoso, Colombia, in 2013 and 2017. He was an assistant lecturer at the same university from 2014 to 2020. Currently, He is pursuing his Ph.D. in Control and Computer Engineering at Politecnico di Torino. His research interests include advanced digital design, computer architectures, parallel architectures and hardware accelerators, artificial intelligence, and test and fault tolerance of digital systems.

Abstract: Deep Neural Networks (DNNs) are fundamental computational structures deployed in a wide range of modern application domains (e.g., data analysis, healthcare, automotive, robotics). These cognitive models demand high-performance computation only provided by hardware accelerator devices. In fact, the Graphics Processing Units (GPUs) stand out over other parallel architectures due to their outstanding performance and programming flexibility. Thus, implementing DNNs on GPU devices is becoming increasingly frequent, even for cutting-edge safety-critical applications (e.g., autonomous and semi-autonomous cars). Unfortunately, modern silicon devices are prone to faults due to several phenomena (e.g., test escapes, process variations, aging, or harsh environments) that may produce permanent defects inside the GPU, thus inducing the DNN to produce wrong results. Consequently, estimating the reliability of these applications under hardware faults is mandatory to fulfill strict safety standards and devise effective hardening solutions. Unfortunately, the traditional fault injection techniques are not applicable for estimating the reliability of a DNN in the face of GPU permanent defects since the programming flexibility of these devices makes it difficult to predict or model their effects correctly at the application level. My research focuses on developing hardware-based fault injection through software propagation to effectively asses the impact on DNNs of permanent defects on GPUs regardless of the software implementation of the neural network.

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Functional Stimuli Generation for Burn-In Test

Mr. Nick Deligiannis
Dept. of Automation and Control Engineering (DAUIN), Politecnico di Torino

Biography:Nick Deligiannis received his bachelor’s and master’s degrees from the Department of Computer Science and Engineering at the University of Ioannina, Greece, in July 2019. In September of the same year, he began working as a research assistant in the CAD Group of the Department of Control and Computer Engineering at Politecnico di Torino. Currently, he is pursuing his Ph.D., working in the same group on subjects related to processor testing and fault tolerance.

Abstract: In the domain of high-reliability applications, Burn-In testing (BI) is always present since it is one of the prime countermeasures against the infant mortality phenomenon. Traditional static BI testing proves to be inefficient for modern circuit designs. The industry employs various BI methods where stimuli are also applied to the devices under test (DUTs) to effectively stress and stimulate all nets of the design. One known industry practice resorts to Design for Testability infrastructures (e.g., scan) and is based on the application of test vectors at low frequencies to excite the DUT as much as possible. Researchers have showcased, however, that the at-speed application of purely functional stress-inducing stimuli can raise the temperature of the DUTs more effectively. The main issue with this approach is that there is not much flexibility in the generation of such stress-inducing stimuli in terms of automation. Hence, a significant amount of manual labor is required by the respective test engineers to come up with the appropriate functional test routines. In my research, I have developed methodologies that streamline the generation of stress-inducing functional routines, particularly for scalar pipelined processors. These methods have yielded notable improvements in the existing practices, contributing positively to the field.

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Reliability and Performance Challenges of Next-Generation Smart Power Battery Management Systems for Electric Mobility

Mr. Amirhossein Ahmadi
Dept. of Electronics and Telecommunication Engineering (DET), Politecnico di Torino

Biography: Amirhossein Ahmadi earned his B.Sc. in Electrical Engineering in 2016 from the Iran University of Science and Technology, and his M.Sc. in the same field in 2019 from Shiraz University of Technology. He became part of the Ph.D. Program in Electrical, Electronics, and Communication Engineering, supported by STMicroelectronics, which focuses on the critical reliability and performance requirements of next-generation electric vehicles, starting from the BMS. His expertise primarily lies in analog and mixed-signal integrated circuits, as well as performing analysis on the susceptibility to Electromagnetic Interference (EMI) of BMS systems.

Abstract: This project discusses the impact of electromagnetic interference (EMI) on the battery management system (BMS) utilized in electric vehicles, with a specific focus on the BMS vertical interface (VIF)—the galvanically isolated data link among various BMS modules. While previous investigations into the BMS’s susceptibility to EMI have been conducted at the system level, this project marks the first attempt to explore the EMI susceptibility of the critical VIF block through transistor-level simulations and tests, considering direct power injection (DPI) and bulk current injection (BCI) test scenarios. Several benchmark parameters are introduced to deepen the understanding of the failure mechanisms noted in simulations and tests and to evaluate how close the VIF comes to failing conditions. The objective is to identify the failure mechanisms and equip IC designers with the knowledge to create VIFs that are inherently immune to EMI, targeting the development of next-generation BMS ICs.

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